Active liquid crystal display panel
An active liquid crystal display panel includes a pixel array, a gate driving circuit, a data driving circuit, and an analog buffer. The gate driving circuit is used for driving M first scan lines where M is a natural number. The analog buffer is coupled to the gate driving circuit and includes M buffer circuits and a regulator. Each buffer circuit drives a corresponding second scan line according to an output signal of a corresponding first scan line of the M first scan lines, and the regulator is used for maintaining at least one reference voltage supplied to the M buffer circuits.
1. An active liquid crystal display panel comprising:
a pixel array comprising a plurality of pixels;
a gate driving circuit for driving M first scan lines, wherein M is a natural number;
a data driving circuit for converting display data into a plurality of data voltages and driving N data lines, wherein an output signal of each data line is used for charging/discharging a pixel corresponding to the data line to a predetermined voltage according to a data voltage of the plurality of data voltages; and
an analog buffer coupled to the gate driving circuit comprising:
M buffer circuits, each buffer circuit comprising:
a P-type thin film transistor having a first terminal, a second terminal directly coupled to a first scan line, and a third terminal directly coupled to a second scan line corresponding to the first scan line, the second scan line being configured to control turning-on and turning-off of a switch coupled to a pixel; and
an N-type thin film transistor having a first terminal directly coupled to the second scan line, a second terminal directly coupled to the first scan line, and a third terminal; and
a regulator comprising:
a first diode having an anode terminal configured to receive a first reference voltage, and a cathode terminal directly coupled to the first terminal of the P-type thin film transistor; and
a second diode having a cathode terminal configured to receive a second reference voltage, and an anode terminal directly coupled to the third terminal of the N-type thin film transistor.
2. The active liquid crystal display panel of claim 1 , wherein when a voltage at the first terminal of the P-type thin film transistor is lower than the first reference voltage, the first diode is turned on.
3. The active liquid crystal display panel of claim 1 , wherein when a voltage at the third terminal of the N-type thin film transistor is higher than the second reference voltage, the second diode is turned on.
4. The active liquid crystal display panel of claim 1 , wherein the regulator is integrated in a low temperature poly-silicon (LTPS) process.
5. An active liquid crystal display panel comprising:
a pixel array comprising a plurality of pixels;
a gate driving circuit for driving M first scan lines, wherein M is a natural number;
a data driving circuit for converting display data into a plurality of data voltages and driving N data lines, wherein an output signal of each data line is used for charging/discharging a pixel corresponding to the data line to a predetermined voltage according to a data voltage of the plurality of data voltages; and
an analog buffer coupled to the gate driving circuit comprising:
M buffer circuits, each buffer circuit consisting of:
a P-type thin film transistor having a first terminal, a second terminal directly coupled to a first scan line, and a third terminal directly coupled to a second scan line corresponding to the first scan line, the second scan line being configured to control turning-on and turning-off of a switch coupled to a pixel; and
an N-type thin film transistor having a first terminal directly coupled to the second scan line, a second terminal directly coupled to the first scan line, and a third terminal; and
a regulator consisting of:
a first diode having an anode terminal configured to receive a first reference voltage, and a cathode terminal directly coupled to the first terminal of the P-type thin film transistor; and
a second diode having a cathode terminal configured to receive a second reference voltage, and an anode terminal directly coupled to the third terminal of the N-type thin film transistor.
6. The active liquid crystal display panel of claim 5 , wherein when a voltage at the first terminal of the P-type thin film transistor is lower than the first reference voltage, the first diode is turned on.
7. The active liquid crystal display panel of claim 5 , wherein when a voltage at the third terminal of the N-type thin film transistor is higher than the second reference voltage, the second diode is turned on.
8. The active liquid crystal display panel of claim 5 , wherein the regulator is integrated in a low temperature poly-silicon (LTPS) process.