Memory system with a programmable refresh cycle
A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.
1. A memory controller comprising:
a table correlating recommended refresh cycle settings to memory system configurations; and
a refresh cycle timing controller configured for:
detecting a memory system configuration, the memory system configuration comprising a density of a memory device;
accessing the table to locate a recommended refresh cycle setting that correlates to the detected memory system configuration;
calculating a refresh cycle time (tRFC) for the memory device in response to the recommended refresh cycle setting and to a base tRFC for the memory device;
calculating a refresh cycle interval (tREFI) for the memory device in response to the recommended refresh cycle setting and to a base tREFI for the memory device; and
transmitting refresh commands to the memory device at the tREFI and waiting for the tRFC to elapse after transmitting each refresh command before transmitting a subsequent command to the memory.
2. The memory controller of claim 1 , wherein the refresh cycle timing controller is further configured for programming the memory device with the calculated tREFI, wherein the calculated tREFI corresponds to a number of memory cells to be refreshed on the memory device in response to receiving each of the refresh commands.
3. The memory controller of claim 1 , wherein the base tRFC is located in a base tRFC table that correlates the memory density to the base tRFC.
4. The memory controller of claim 1 , wherein the base tREFI is located in a base tREFI table that correlates the memory density to the base tREFI.
5. The memory controller of claim 1 , wherein the detected memory system configuration comprises a number of ranks.
6. The memory controller of claim 1 , wherein the memory device is a dynamic random access memory (DRAM) device.
7. The memory controller of claim 1 , wherein the detecting the memory system configuration comprises reading a serial presence detect (SPD).
8. A method for refreshing a memory device, the method comprising:
detecting a memory system configuration, the detecting at a memory controller and the memory system configuration comprising a density of a memory device;
accessing a table that correlates recommend refresh cycle settings to memory system configurations to locate a recommended refresh cycle setting that correlates to the detected memory system configuration;
calculating a refresh cycle time (tRFC) for the memory device in response to the recommended refresh cycle setting and to a base tRFC for the memory device;
calculating a refresh cycle interval (tREFI) for the memory device in response to the recommended refresh cycle setting and to a base tREFI for the memory device; and
transmitting refresh commands to the memory device at the tREFI and waiting for the tRFC to elapse after transmitting each refresh command before transmitting a subsequent command to the memory.
9. The method of claim 8 further comprising programming the memory device with the calculated tREFI, wherein the calculated tREFI corresponds to a number of memory cells to be refreshed on the memory device in response to receiving each of the refresh commands.
10. The method of claim 8 , wherein the base tRFC is located in a base tRFC table that correlates the memory density to the base tRFC.
11. The method of claim 8 , wherein the base tREFI is located in a base tREFI table that correlates the memory density to the base tREFI.
12. The method of claim 8 , wherein the detected memory system configuration comprises a number of ranks.
13. The method of claim 8 , wherein the memory device is a dynamic random access memory (DRAM) device.