Encoded read-only memory (ROM) bitcell, array, and architecture
View Patent ↗Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.
1. A memory block, comprising:
a first memory array, including a first memory cell;
a second memory array, including a second memory cell;
a first common pull down (CPD) line selectively controlled to access the first memory cell;
a second CPD line selectively controlled to access the second memory cell; and
a shared bit line set, coupled to the first memory array and the second memory array, configured to read the first memory cell and the second memory cell.
2. The memory block of claim 1 , further comprising:
a first CPD driver configured to drive the first CPD line; and
a second CPD driver configured to drive the second CPD line.
3. The memory block of claim 2 , further comprising:
a block input/output (I/O) circuitry configured to decode the shared bit line set to generate a data signal.
4. The memory block of claim 3 , wherein the first CPD driver and the second CPD driver are placed between the first memory array and the second memory array, thereby enabling reduction of respective lengths of the first CPD line and the second CPD line.
5. The memory block of claim 2 , wherein the first CPD driver and the second CPD driver are configured to drive the first CPD line and the second CPD line such that the shared bit line set reads only one of the first memory cell and the second memory cell at a given time.
6. The memory block of claim 1 , wherein at least one of the first and second memory cells comprises:
a transistor having drain, source, and gate terminals; and
a plurality of program nodes, each of said program nodes charged to a pre-Determined voltage and coupled to a respective bit line of the shared bit line set.
7. The memory block of claim 6 , wherein at most one of the plurality of program nodes is coupled to the drain terminal of the transistor.
8. A memory having a plurality of rows of memory cells, comprising:
a plurality of memory blocks, each including respective rows of the plurality of rows of memory cells of the memory,
wherein each of the plurality of memory blocks comprises a dedicated respective bit line set, a common pull down (CPD) line set, and block input/output (I/O) circuitry, wherein the CPD line set is selectively asserted to access a memory cell of said each of the plurality of memory blocks.
9. The memory of claim 8 , wherein at least one memory block of the plurality of memory blocks comprises:
a first memory array, including a first memory cell;
a second memory array, including a second memory cell;
a first common pull down (CPD) line configured to access the first memory cell;
a second CPD line configured to access the second memory cell; and
a shared bit line set, coupled to the first memory array and the second memory array, configured to read the first memory cell and the second memory cell.
10. The memory of claim 9 , wherein the at least one memory block further comprises:
a first CPD driver configured to drive the first CPD line; and
a second CPD driver configured to drive the second CPD line.
11. The memory of claim 8 , wherein each of the memory cells has a respective row address and a respective column address, and
wherein same row address memory cells of the memory cells share a common word line.
12. A memory cell, comprising:
a transistor having drain, source, and gate terminals; and
a plurality of program nodes, each of the plurality of program nodes charged to a pre-determined voltage,
wherein at most one of the plurality of program nodes is selectively coupled to the drain terminal of the transistor to program the memory cell to store at least one information bit.
13. The memory cell of claim 12 . wherein each of the plurality of program nodes is coupled to a respective one of a plurality of bit lines.
14. The memory cell of claim 12 , wherein exactly one of the plurality of program nodes is coupled to the drain terminal of the transistor.
15. The memory cell of claim 12 , wherein none of the plurality of program nodes is coupled to the drain terminal of the transistor.
16. The memory cell of claim 12 , wherein a value of the at least one information bit stored in the memory cell is determined based on which, if any, of the plurality of program nodes is coupled to the drain terminal of the transistor.
17. The memory cell of claim 12 , wherein the program nodes are charged to the pre-determined voltage at manufacture time.
18. The memory cell of claim 12 , wherein the plurality of program nodes comprise four program nodes, and wherein at most one of the four program nodes is coupled to the drain terminal of the transistor to program the memory cell to store two information bits.
19. The memory cell of claim 12 , wherein the plurality of program nodes comprise three program nodes, and wherein at most one of the three program nodes is coupled to the drain terminal of the transistor to program the memory cell to store two information bits.
20. The memory cell of claim 12 , wherein the plurality of program nodes comprise seven program nodes, and wherein at most one of the seven program nodes is coupled to the drain terminal of the transistor to program the memory cell to store three information bits.