Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method
A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.
1. A semiconductor device comprising:
a wafer having a front face and a rear face and in which is formed a main blind hole in its front face;
a capacitor formed in the main blind hole which comprises:
a conductive outer layer covering a side wall and a bottom of the main blind hole and forming an outer electrode,
a dielectric intermediate layer covering the conductive outer layer and forming a dielectric membrane, and
a filling conductive material, at least partially filling the main blind hole and forming an inner electrode;
a secondary rear hole formed in the rear face of the wafer, at least partially revealing a bottom surface of the outer electrode; and
a rear electrical connection on the rear face of the wafer and in electrical contact with the bottom surface of the outer electrode through the secondary rear hole.
2. The device according to claim 1 , also comprising:
a main through hole passing through the wafer and situated at a distance from the main blind hole containing the capacitor,
a conductive material filling the main through hole so as to form an electrical connection through via having a front end situated in a plane of the front face of the wafer and a rear end situated in a plane of the rear face of the wafer.
3. The device according to claim 2 , in which a diameter of the main through hole containing the electrical connection through via is greater than a diameter of the blind hole containing the capacitor.
4. The device according to claim 2 , wherein the rear electrical connection extends to link the electrical connection through via to the outer electrode of the capacitor.
5. The device according to claim 2 , further comprising a front electrical connection linking the electrical connection through via and a front external electrical connection element.
6. The device according to claim 2 , further comprising a front electrical connection linking the electrical connection through via to integrated circuits formed on a surface of the wafer.
7. The device according to claim 1 , also comprising:
another main blind hole situated at a distance from the main blind hole containing the capacitor,
a filling conductive material filling this another main hole so as to form an electrical connection via having a front end situated in a plane of the front face of the wafer,
another secondary rear hole formed in the rear face of the wafer, at least partially revealing a bottom of the electrical connection via, and
another rear electrical connection on the rear face of the wafer and in electrical contact with the bottom of the electrical connection via through the another secondary rear hole.
8. The device according to claim 7 , wherein the further comprising a rear electrical connection extends to link the electrical connection via to the outer electrode of the capacitor.
9. The device according to claim 7 , further comprising a front electrical connection linking the electrical connection via and a front external electrical connection element.
10. The device according to claim 7 , further comprising a front electrical connection linking the electrical connection via to integrated circuits formed on a surface of the wafer.
11. The device according to claim 1 , wherein the rear electrical connection extends to link linking the outer electrode of the capacitor to a rear external electrical connection element.
12. The device according to claim 1 , further comprising a front electrical connection linking the inner electrode of the capacitor and a front external electrical connection element.
13. The device according to claim 1 , in which the wafer comprises:
a substrate on a front face of which are formed integrated circuits, and
a dielectric layer formed on the front face of the substrate.
14. The device according to claim 13 , comprising a front electrical connection linking the inner electrode of the capacitor and the integrated circuits.
15. A method for fabricating a semiconductor device containing a capacitor, comprising:
producing a main blind hole in a front face of a wafer;
successively depositing in the main blind hole a first conductive layer, a dielectric layer and a second conductive layer at least partially filling the main blind hole to form said capacitor;
producing a secondary rear hole in a rear face of the wafer to at least partially reveal a bottom of the portion of the first conductive layer situated in the main blind hole; and
forming a rear electrical connection on the rear face of the wafer and in the secondary rear hole to make electrical contact to the revealed bottom portion of the first conductive layer.
16. The method of claim 15 , further comprising:
producing a main through hole passing through the wafer and situated at a distance from the main blind hole containing the capacitor,
filling the main through hole with a conductive material so as to form an electrical connection through via having a front end situated in a the plane of the front face of the wafer and a rear end situated in a plane of the rear face of the wafer.
17. The method of claim 16 , further comprising forming said rear electrical connection on the rear face of the wafer to extend between the electrical connection through via and the revealed bottom portion of the first conductive layer.
18. The method of claim 15 , further comprising:
forming another main blind hole situated at a distance from the main blind hole containing the capacitor,
filling the another main blind hole with a conductive material filling so as to form an electrical connection via having a front end situated in a plane of the front face of the wafer, and
producing another secondary rear hole in the rear face of the wafer, at least partially revealing a bottom of the electrical connection via.
19. The method of claim 18 , further comprising forming said rear an electrical connection on the rear face of the wafer to extend between the revealed bottom of the electrical connection via and the revealed bottom portion of the first conductive layer.
20. A method for fabricating a semiconductor device containing a capacitor, comprising:
producing, in a front face of a wafer comprising a substrate provided with front integrated circuits and a front dielectric layer, a first main blind hole and a second main blind hole;
successively depositing in the first main blind hole a first conductive layer, a dielectric layer and a second conductive layer at least partially filling the first main blind hole;
at least partially filling the second main blind hole with a conductive material;
reducing a thickness of the wafer by removing a rear portion of this wafer to transform the first and second main blind holes into first and second main holes passing through a reduced thickness wafer;
depositing, on a rear face of the reduced thickness wafer, a dielectric rear layer;
reducing a thickness of the dielectric rear layer to form an electrical connection via by exposing the conductive material of the second main blind hole without exposing a bottom of the portion of the first conductive layer situated in the first main blind hole;
producing a secondary rear hole in the reduced thickness dielectric rear layer to at least partially reveal a bottom of the portion of the first conductive layer situated in the first main blind hole; and
forming a rear electrical connection on a rear face of the reduced thickness dielectric rear layer and in the secondary rear hole to make electrical contact to the revealed bottom portion of the first conductive layer.
21. The method according to claim 20 , in which the conductive material at least partially filing the second main blind hole comprises the first and second conductive layers.
22. The method according to claim 21 , in which the dielectric layer does not extend into the second main blind hole.
23. The method according to claim 20 , further comprising: producing front and rear electrical connections to the capacitor.
24. The method according to claim 20 , further comprising: producing front and rear electrical connections to the electrical connection via.