IP Library Granted Patent US 8,877,521
Granted Patent B2
US 8,877,521 · App. 14/226,816 · Granted Nov 4, 2014

Semiconductor ferroelectric device, manufacturing method for the same, and electronic device

Inventor: Hiroshi Tanabe (Tokyo, JP)
Assignee: Gold Charm Limited
H01L29/66742H01L29/6684H01L28/55H01L27/11502H01L27/1214H01L27/13
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,877,521
App. No.
14/226,816
Granted
Nov 4, 2014
Kind
B2
Abstract

A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode.

Claims (21)

1. A manufacturing method for a semiconductor device, said method comprising:

forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask;

forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and

forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer;

forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film;

forming a ferroelectric layer on the lower electrode; and

forming an upper electrode on the ferroelectric layer, wherein a hydrogen concentration of the thin film transistor is higher than a hydrogen concentration off the ferroelectric layer, and

wherein the semiconductor device further comprises a protective oxide film between at least one of the source region, the drain region, the interlayer dielectric film, and the channel region, and the insulating substrate, wherein the channel region comprises a plurality of Si—H bonds.

2. A manufacturing method for a semiconductor device, comprising:

forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film and forming source/drain regions and a channel region by implanting ions into the polysilicon thin film by using the gate electrode as a mask;

forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film;

forming a silicon hydronitride film so as to cover the interconnection layer;

forming a lower electrode on this silicon hydronitride film;

forming a ferroelectric layer on the lower electrode; and

forming an upper electrode on the ferroelectric layer and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film,

wherein a hydrogen concentration of the polysilicon thin film, the gate electrode, the source/drain regions, and the channel region are higher than a hydrogen concentration of the ferroelectric layer, and

wherein the semiconductor device further comprises a protective oxide film between at least one of the source region, the drain region, the interlayer dielectric film, and the channel region, and the insulating substrate, wherein the channel region comprises a plurality of Si—H bonds.

3. The manufacturing method for a semiconductor device according to claim 1 , wherein the silicon hydronitride film is formed by a plasma CVD (Chemical Vapor Deposition) (vapor growth) method.

4. The manufacturing method for a semiconductor device according to claim 2 , wherein the silicon hydronitride film is formed by plasma CVD (Chemical Vapor Deposition) (vapor growth) method.

5. The manufacturing method for a semiconductor device according to claim 1 , wherein a temperature of the polysilicon thin film does not become higher than 350° C. in the steps after the forming the silicon hydronitride layer.

6. The manufacturing method for a semiconductor device according to claim 2 , wherein the temperature of the polysilicon thin film does not become higher than 350° C. in the steps after the forming the silicon hydronitride layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2023
From: GOLD CHARM LIMITED
To: HANNSTAR DISPLAY CORPORATION
Reel/Frame 063394/0342 →
Priority Claims (1)
JP 2004-187036 · Jun 24, 2004 · national
Continuity (3)
Division 12923281 · Sep 13, 2010
Division 11159097 · Jun 23, 2005
Related Publication 20140206107A1 · Jul 24, 2014