Digitally controlled oscillator with thermometer sigma delta encoded frequency control word
View Patent ↗Systems and methods for generating a thermometer sigma delta encoded frequency control word for controlling a digitally controlled oscillator in accordance with embodiments of the invention are disclosed. In one embodiment, an all digital phase locked loop for generating an output clock signal includes a thermometer pulse coder configured to generate a frequency control word (FCW) that includes thermometer coded signals and a pulse modulated dither signal, and transmit the pulse modulated dither signal over a selected FCW signal line and transmit the thermometer coded signals over other FCW signal lines, and a digitally controlled oscillator to receive a FCW comprising a combined thermometer and pulse modulated signal and generate an output clock signal.
1. A method for generating an output clock signal from a reference clock signal using an all digital phase locked loop (ADPLL), the method comprising:
generating a frequency control word from a binary encoded frequency control word using a thermometer pulse coder, where the thermometer pulse coder includes a plurality of frequency control word signal lines and the frequency control word includes a plurality of thermometer coded signals and a pulse modulated dither signal; and
selecting, using the thermometer pulse coder, one of the plurality of frequency control word signal lines and transmit the pulse modulated dither signal over the selected frequency control word signal line and transmit the thermometer coded signals over a plurality of the other frequency control word signal lines;
receiving by a digitally controlled oscillator a frequency control word comprising a combined thermometer and pulse modulated signal via the plurality of frequency control world signal lines and generating an output clock signal at a frequency determined using at least the frequency control word;
receiving by a feedback divider the output clock signal from the digitally controlled oscillator and generating a feedback signal; and
receiving by a phase detector a reference clock signal and a feedback signal from the feedback divider and generating a phase error signal, which is provided to a digital loop filter configured to generate a binary encoded frequency control word that is input to the thermometer pulse coder.
2. The method of claim 1 , wherein the thermometer pulse coder further comprises a thermometer coder and a pulse modulation coder; and
the method further comprises generating a plurality of thermometer coded signals using the thermometer coder and generating a pulse modulated dither signal using the pulse modulation coder.
3. The method of claim 2 , wherein generating a pulse modulated dither signal using the pulse modulation coder comprises generating a sigma delta coded dither signal using sigma delta coding.
4. The method of claim 2 , wherein the thermometer pulse coder further comprises a plurality of line encoders and the method further comprises:
receiving at least two of the plurality of thermometer coded signals and the pulse modulated dither signal at the plurality of line encoders; and
determining, based upon the values on the received thermometer coded signals using the plurality of line encoders, whether to output one of the received thermometer coded signals or the received pulse modulated dither signal.
5. The method of claim 4 , further comprising:
receiving a first of the plurality of thermometer coded signals and a second of the plurality of thermometer coded signals at an AND gate in at least one of the line encoders; and
receiving the output of the AND gate, the first of the plurality of thermometer coded signals, and the pulse modulated dither signal at a MUX in the least one of the line encoders, and outputting using the MUX either the first of the plurality of thermometer coded signals or the pulse modulated dither signal based upon the output of the AND gate.
6. The method of claim 1 , wherein the phase detector is a bang-bang phase detector.
7. The method of claim 1 , further comprising receiving the output clock signal from the digitally controlled oscillator and scaling the frequency of the output clock signal using a prescaler.
8. The method of claim 7 , wherein the feedback divider is a programmable integer N feedback divider.
9. The method of claim 8 , wherein the received reference clock signal is 25 Hz, the digitally controlled oscillator produces an output frequency 240 times greater than the reference clock signal, the prescaler divides the output clock signal frequency by two, and the feedback divider multiplies the received output clock signal by 2/240.
10. The method of claim 1 wherein the digital loop filter comprises:
an integral phase error path that is configured to receive the phase error from the phase detector and has an adjustable gain; and
a frequency error path that is configured to receive the reference clock signal and a signal from the feedback divider and has an adjustable gain.
11. The method of claim 1 , further comprising controlling zone frequency tuning using a state machine.
12. The method of claim 1 , wherein the digitally controlled oscillator is an inductor-capacitor oscillator.
13. The method of claim 1 , wherein the digitally controlled oscillator comprises a zone capacitor array, a fine frequency tuning capacitor array, and a proportional tuning capacitor array.
14. The method of claim 13 , wherein the zone capacitor array comprises metal-to-metal capacitors.
15. The method of claim 13 , wherein the fine frequency tuning capacitor array comprises NMOS varactors.
16. The method of claim 13 , wherein the proportional tuning capacitor array comprises metal-to-metal capacitors and binary weighted NMOS varactors.
17. The method of claim 13 , wherein the digitally controlled oscillator further comprises a proportional-to-absolute-temperature circuit.