IP Library Granted Patent US 8,917,471
Granted Patent B1
US 8,917,471 · App. 14/105,603 · Granted Dec 23, 2014

Power management for data storage device

Inventors: Zaihas Amri Fahdzan Hasfar (Selangor, MY); Choo-Bhin Ong (Foothill Ranch, CA); Jonathan K. Cheng (Mission Viejo, CA)
Assignee: Western Digital Technologies, Inc.
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Quick Facts
Patent No.
US 8,917,471
App. No.
14/105,603
Granted
Dec 23, 2014
Kind
B1
Abstract

A data storage device (DSD) enters a high spindle suppression (HSS) mode to reduce instances of rotation of a spindle motor of the DSD during the HSS mode. When a read command is received from a host to read requested data from the DSD in the HSS mode, it is determined whether the requested data is not stored in a solid state memory of the DSD. If it is determined that the requested data is not stored in the solid state memory, the spindle motor is controlled to rotate a disk of the DSD. The requested data is read from the disk and stored in the solid state memory before completing transfer of the requested data to the host.

Claims (58)

1. A data storage device (DSD), comprising:

a disk for storing data;

a spindle motor for rotating the disk;

a solid state memory for storing data; and

a controller configured to:

enter a high spindle suppression (HSS) mode to reduce instances of rotation of the spindle motor during the HSS mode;

receive a read command from a host to read requested data from the DSD while the DSD is in the HSS mode;

determine whether the requested data is not stored in the solid state memory; and

when it is determined that the requested data is not stored in the solid state memory:

control the spindle motor to rotate the disk;

read the requested data from the disk; and

store the requested data in the solid state memory before completing transfer of the requested data to the host.

2. The DSD of claim 1 , wherein the controller is further configured to:

receive a write command from the host to write host data to the disk of the DSD while the DSD is in the HSS mode;

determine whether there is an address allocated for the host data in the solid state memory; and

if it is determined there is not an address allocated for the host data, write the host data to a predetermined space of the solid state memory.

3. The DSD of claim 1 , wherein the controller is further configured to enter the HSS mode based on an indication received from the host.

4. The DSD of claim 3 , wherein the indication received from the host indicates that the host is entering a low power state.

5. The DSD of claim 3 , wherein the indication received from the host indicates that the host is entering a fresh data collection cycle where the host periodically retrieves data from a network for storage in the DSD.

6. The DSD of claim 1 , wherein the controller is further configured to enter the HSS mode based on data access activity by the host.

7. The DSD of claim 6 , wherein the controller is further configured to enter the HSS mode by identifying an address corresponding to data requested by the host as associated with a startup of the DSD or a startup of the host.

8. The DSD of claim 1 , wherein the controller is further configured to exit the HSS mode based on an indication received from the host.

9. A method for operating a data storage device (DSD), the method comprising:

entering a high spindle suppression (HSS) mode to reduce instances of rotation of a spindle motor of the DSD during the HSS mode;

receiving a read command from a host to read requested data from the DSD while the DSD is in the HSS mode;

determining whether the requested data is not stored in a solid state memory of the DSD; and

when it is determined that the requested data is not stored in the solid state memory:

controlling the spindle motor to rotate a disk of the DSD;

reading the requested data from the disk; and

storing the requested data in the solid state memory before completing transfer of the requested data to the host.

10. The method of claim 9 , further comprising:

receiving a write command from the host to write host data to the disk of the DSD while the DSD is in the HSS mode;

determining whether there is an address allocated for the host data in the solid state memory; and

if it is determined there is not an address allocated for the host data, writing the host data to a predetermined space of the solid state memory.

11. The method of claim 9 , further comprising entering the HSS mode based on an indication received from the host.

12. The method of claim 11 , wherein the indication received from the host indicates that the host is entering a low power state.

13. The method of claim 11 , wherein the indication received from the host indicates that the host is entering a fresh data collection cycle where the host periodically retrieves data from a network for storage in the DSD.

14. The method of claim 9 , further comprising entering the HSS mode based on data access activity by the host.

15. The method of claim 14 , further comprising entering the HSS mode by identifying an address corresponding to data requested by the host as associated with a startup of the DSD or a startup of the host.

16. The method of claim 9 , further comprising exiting the HSS mode based on an indication received from the host.

17. A non-transitory computer readable medium storing computer-executable instructions, wherein when the computer executable instructions are executed by a processor or a controller, the computer executable instructions cause a data storage device (DSD) to:

enter a high spindle suppression (HSS) mode to reduce instances of rotation of a spindle motor of the DSD during the HSS mode;

receive a read command from a host to read requested data from the DSD while the DSD is in the HSS mode;

determine whether the requested data is not stored in a solid state memory of the DSD; and

when it is determined that the requested data is not stored in the solid state memory:

control the spindle motor to rotate a disk of the DSD;

read the requested data from the disk; and

store the requested data in the solid state memory before completing transfer of the requested data to the host.

18. The computer readable medium of claim 17 , wherein the computer-executable instructions further cause the DSD to:

receive a write command from the host to write host data to the disk of the DSD while the DSD is in the HSS mode;

determine whether there is an address allocated for the host data in the solid state memory; and

if it is determined there is not an address allocated for the host data, write the host data to a predetermined space of the solid state memory.

19. The computer readable medium of claim 17 , wherein the computer-executable instructions further cause the DSD to enter the HSS mode based on an indication received from the host.

20. The computer readable medium of claim 19 , wherein the indication received from the host indicates that the host is entering a low power state.

21. The computer readable medium of claim 19 , wherein the indication received from the host indicates that the host is entering a fresh data collection cycle where the host periodically retrieves data from a network for storage in the DSD.

22. The computer readable medium of claim 17 , wherein the computer-executable instructions further cause the DSD to enter the HSS mode based on data access activity by the host.

23. The computer readable medium of claim 22 , wherein the computer-executable instructions further cause the DSD to enter the HSS mode by identifying an address corresponding to data requested by the host as associated with a startup of the DSD or a startup of the host.

24. The computer readable medium of claim 17 , wherein the computer-executable instructions further cause the DSD to exit the HSS mode based on an indication received from the host.

Assignments (9)
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2014
From: HASFAR, ZAIHAS AMRI FAHDZAN; ONG, CHOO-BHIN; CHENG, JONATHAN K.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 033577/0128 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2014
From: HASFAR, ZAIHAS AMRI FAHDZAN; ONG, CHOO-BHIN; CHENG, JONATHAN K.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 032976/0565 →
Continuity (1)
Provisional Application 61897063 · Oct 29, 2013