IP Library Granted Patent US 8,921,147
Granted Patent B2
US 8,921,147 · App. 13/966,663 · Granted Dec 30, 2014

Method and apparatus providing multi-step deposition of thin film layer

Inventors: Arnold Allenic (Ann Arbor, MI); Zhigang Ban (Perrysburg, OH); John Barden (Ottawa Hills, OH); Benjamin Milliron (Toledo, OH); Rick C. Powell (Ann Arbor, MI)
Assignee: First Solar, Inc.
H01L31/1828H01L21/02562C23C14/228H01L21/02573C23C14/246H01L21/02581C23C14/243H01L21/02631H01L21/02557
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Quick Facts
Patent No.
US 8,921,147
App. No.
13/966,663
Granted
Dec 30, 2014
Kind
B2
Abstract

A multi-stage method and apparatus for vaporizing and depositing a tellurium containing semiconductor material on a substrate.

Claims (59)

1. A method of multi-stage vapor deposition of a tellurium containing material, the method comprising:

flowing a first solid tellurium containing semiconductor material into a first heated chamber which produces a first tellurium containing material vapor, wherein the first heated chamber is heated to a temperature less than or equal to 1050° C.;

depositing the first tellurium containing material vapor onto a substrate as a first tellurium containing semiconductor material layer;

flowing a second solid state tellurium containing semiconductor material into a second heated chamber which produces a second tellurium containing material vapor, wherein the second heated chamber is heated to a temperature less than or equal to 1050° C.; and,

depositing the second tellurium containing material vapor as a second tellurium containing material layer onto the deposited first tellurium containing material layer.

2. A method as in claim 1 , wherein the first and second solid tellurium containing semiconductor materials are the same material.

3. The method as in claim 1 , wherein the first and second solid tellurium containing semiconductor materials are selected from the group consisting of binary tellurium containing semiconductor materials.

4. The method as in claim 1 , wherein the first and second solid tellurium containing semiconductor materials are selected from the group consisting of ternary tellurium containing semiconductor materials.

5. The method as in claim 1 , wherein the first and second solid tellurium containing semiconductor materials are the same material and are selected from the group consisting of binary tellurium containing semiconductor materials.

6. The method as in claim 1 , wherein the first and second solid tellurium containing semiconductor materials are the same material and are selected from the group consisting of ternary tellurium containing semiconductor materials.

7. The method as in claim 1 , wherein the deposited first and second tellurium containing semiconductor material layers form an integrated material layer.

8. The method as in claim 7 , wherein first and second tellurium containing material layers form an absorber layer of a photovoltaic device.

9. The method as in claim 5 , wherein the first and second solid tellurium containing semiconductor materials comprise CdTe.

10. The method as in claim 1 , wherein the first and second solid tellurium containing semiconductor materials are in powdered form.

11. The method as in claim 7 , wherein the integrated material layer has an impurity concentration of less than or equal to about 1e18/cm 3 .

12. The method as in claim 7 , wherein the integrated material layer has an impurity concentration within the range of about 1e16/cm 3 to about 1e18/cm 3 .

13. The method as in claim 11 , wherein the impurity comprises one or more impurities selected from the group consisting of tantalum (Ta), cobalt (Co), copper (Cu), vanadium (Va), iron (Fe), antimony (Sb), zirconium (Zr), tin (Sn), silicon (Si) and aluminum (Al).

14. The method as in claim 12 , wherein the impurity comprises silicon.

15. The method as in claim 1 , wherein the first and second heated chambers are within a common deposition housing, the method further comprising transporting substrates through the common deposition housing to sequentially receive vapor generated by the first and second heated chambers.

16. The method as in claim 1 , wherein the first and second heated chambers are each within a respective deposition housing, the method further comprising transporting substrates sequentially through the respective deposition housings.

17. The method as in claim 16 , wherein the thickness of the first and second deposited tellurium containing semiconductor layers is about the same.

18. The method as in claim 16 , wherein the thickness of the first and second deposited tellurium containing semiconductor layers is not the same.

19. The method as in claim 1 , further comprising a third heated chamber associated with at least one of the first and second heated chambers for receiving and vaporizing a third solid tellurium containing semiconductor, wherein the third heated chamber is commonly connected with the at least one of the first and second chambers to a vapor distributor which receives vapor from each and directs the received vapor onto the substance to form a tellurium containing semiconductor material layer on the substrate as at least one of the first and second tellurium containing material layers.

20. The method as in claim 1 , wherein the first and second solid tellurium containing semiconductor materials each comprise CdS x Te 1-x , where x is greater than zero and less than one.

21. The method as in claim 1 , wherein the first and second solid tellurium containing semiconductor materials each comprise ZnTe.

22. The method as in claim 1 , wherein the first and second solid tellurium containing materials each comprise CdZn x Te 1-x , where x is greater than zero and less than one.

23. A method of multi-stage vapor deposition of a tellurium containing semiconductor material, the method comprising:

flowing a plurality of solid tellurium containing materials respectively into each of a plurality of heated chambers which respectively produce a tellurium containing material vapor;

directing the respective vapor from each of the plurality of heated chambers sequentially onto a substrate to form a plurality of sequentially deposited material layers; and

controlling the temperature of each of the heated chambers to be less than or equal to 1050° C. such that concentration of an impurity in the deposited material is less than or equal to about 1 e18/cm 3 .

24. The method as in claim 23 , wherein the impurity comprises one or more impurities selected from the group consisting of tantalum (Ta), cobalt (Co), copper (Cu), vanadium (Va), iron (Fe), antimony (Sb), zirconium (Zr), tin (Sn), silicon (Si) and aluminum (Al).

25. The method as in claim 23 , wherein the impurity is silicon (Si) having a concentration in the deposited material within the range of about 1e16/cm 3 to about 1e18/cm 3 .

26. The method as in claim 23 , wherein the plurality of solid tellurium containing semiconductor materials are selected from the group consisting of binary tellurium containing semiconductor materials.

27. The method as in claim 23 , wherein the plurality of solid tellurium containing semiconductor materials are selected from the group consisting of ternary tellurium containing semiconductor materials.

28. The method as in claim 23 , wherein the plurality of heated chambers are respectively connected to a plurality of vapor distributors which receive vapor from a respective heated chamber and directs the received vapor onto the substance.

29. The method as in claim 23 , wherein the plurality of solid tellurium containing semiconductor materials each comprise CdTe.

30. The method as in claim 23 , wherein the plurality of solid tellurium containing semiconductor materials each comprise CdS x Te 1-x , where x is greater than zero and less than one.

31. The method as in claim 23 , wherein the plurality of solid tellurium containing semiconductor materials each comprise ZnTe.

32. The method as in claim 23 , wherein the plurality of solid tellurium containing materials each comprise CdZn x Te 1-x , where x is greater than zero and less than one.

33. An apparatus for depositing a tellurium containing semiconductor material, the apparatus comprising:

a plurality of heated chambers each for vaporizing a respective solid tellurium containing semiconductor material, the heated chambers each producing a respective vaporized tellurium containing semiconductor material;

a plurality of vapor flow paths respectively associated with the plurality of heated chambers for respectively and sequentially depositing a respective vaporized tellurium containing semiconductor material on a substrate as a plurality of sequentially deposited material layers; and

a temperature controller for controlling heating of each of the plurality of heated chambers to a temperature less than or equal to 1050° C.

34. The apparatus as in claim 33 , wherein the plurality of heated chambers are in a common deposition housing.

35. The apparatus as in claim 33 , wherein the plurality of heated chambers are in respective deposition housings.

36. The apparatus as in claim 33 , wherein the respective solid tellurium containing semiconductor materials are the same material.

37. The apparatus as in claim 33 , wherein the respective solid tellurium containing semiconductor materials are selected from the group consisting of binary tellurium containing semiconductor materials.

38. The apparatus as in claim 33 , wherein the respective solid tellurium containing semiconductor materials are selected from the group consisting of ternary tellurium containing semiconductor materials.

39. The apparatus as in claim 33 , wherein the respective vaporized tellurium containing semiconductor materials each produce a deposited layer on the substrate containing an impurity, and

wherein the temperature controller controls the heating to keep the impurity concentration in each deposited layer to less than about 1e18/cm 3 .

40. The apparatus as in claim 33 , wherein the respective vaporized tellurium containing semiconductor materials each produce a deposited layer on the substrate containing silicon, and

wherein the temperature controller controls the heating to keep the silicon in the deposited layer to a concentration in each deposited layer within the range of about 1e16/cm 3 to about 1e18/cm 3 .

41. The apparatus as in claim 39 , wherein the impurity comprises one or more impurities selected from the group consisting of tantalum (Ta), cobalt (Co), copper (Cu), vanadium (Va), iron (Fe), antimony (Sb), zirconium (Zr), tin (Sn), silicon (Si) and aluminum (Al).

42. The apparatus as in claim 33 , wherein the respective solid tellurium containing materials comprise CdTe.

43. The apparatus as in claim 33 , wherein the respective solid tellurium containing materials comprise ZnTe.

44. The apparatus as in claim 33 , wherein the respective solid tellurium containing materials comprise CdS x Te 1-x , where x is greater than zero and less than one.

45. The apparatus as in claim 33 , wherein the respective solid tellurium containing materials comprise CdZn x Te 1-x , where x is greater than zero and less than one.

46. The apparatus as in claim 33 , further comprising an additional heated chamber associated with one of the plurality of heated chambers for receiving and vaporizing a solid tellurium containing semiconductor material wherein vapor from the additional heated chamber and the one of the plurality of heated chambers is provided by a flow distributor commonly connected to the additional and the one of heated chambers.

47. The method as in claim 23 , further comprising an additional heated chamber associated with at least one of the plurality of heated chambers for receiving and vaporizing a third solid tellurium, the additional heated chamber and the at least one of the plurality of heated chambers being commonly connected to a vapor distribution which receives vapor from each and directs the received vapor onto the substrate.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Feb 13, 2026
From: JPMORGAN CHASE BANK, N.A.
To: FIRST SOLAR, INC.
Reel/Frame 074858/0364 →
SECURITY INTEREST Recorded Jul 10, 2023
From: FIRST SOLAR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 064237/0462 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 15, 2021
From: JPMORGAN CHASE BANK, N.A.
To: FIRST SOLAR, INC.
Reel/Frame 058132/0566 →
PATENT SECURITY AGREEMENT Recorded Jul 12, 2017
From: FIRST SOLAR, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 043177/0581 →
Continuity (2)
Provisional Application 61684158 · Aug 17, 2012
Related Publication 20140051206A1 · Feb 20, 2014