IP Library Granted Patent US 8,921,867
Granted Patent B2
US 8,921,867 · App. 14/130,940 · Granted Dec 30, 2014

Thin-film transistor, display panel, and method for producing a thin-film transistor

Inventors: Yuko Okumoto (Osaka, JP); Akihito Miyamoto (Osaka, JP)
Assignee: Panasonic Corporation
H01L51/0529H01L29/786H01L51/004H01L27/3274H01L27/3262H01L51/0533H01L51/0541H01L51/0545H01L2251/5315H01L51/0037
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Quick Facts
Patent No.
US 8,921,867
App. No.
14/130,940
Granted
Dec 30, 2014
Kind
B2
Abstract

A thin-film transistor including: a gate electrode that is located above a substrate; a gate insulating layer that faces the gate electrode; a partition that defines an opening and has higher liquid repellency than liquid repellency of the gate insulating layer, the opening having a surface of the gate insulating layer therewithin; a semiconductor layer that faces the gate electrode with the gate insulating layer interposed therebetween and is formed within the opening by an application method; a source electrode and a drain electrode that are electrically connected to the semiconductor layer; and an intermediate layer that is made of the same material as a material of the partition and is located between the gate insulating layer and the semiconductor layer, wherein the intermediate layer is discretely present above the gate insulating layer.

Claims (54)

1. A thin-film transistor comprising:

a gate electrode that is located above a substrate;

a gate insulating layer that faces the gate electrode;

a partition that defines an opening and has higher liquid repellency than liquid repellency of the gate insulating layer, a surface of the gate insulating layer being located in the opening;

a semiconductor layer that faces the gate electrode with the gate insulating layer interposed therebetween, and is formed within the opening by an application method;

a source electrode and a drain electrode that are electrically connected to the semiconductor layer; and

an intermediate layer that is made of the same material as a material of the partition and is located between the gate insulating layer and the semiconductor layer,

wherein the intermediate layer is discretely present above the gate insulating layer.

2. The thin-film transistor according to claim 1 ,

wherein the gate insulating layer on which the intermediate layer is formed has a contact angle against water that is smaller than a contact angle against water of the partition.

3. The thin-film transistor according to claim 1 ,

wherein the gate insulating layer on which the intermediate layer is formed has a contact angle against water of 40 degrees or more and 70 degrees or less in at least a part of a region of the intermediate layer that is in contact with the semiconductor layer.

4. The thin-film transistor according to claim 1 ,

wherein the intermediate layer is also located between the semiconductor layer and at least one of the source electrode and the drain electrode, and

the intermediate layer is discretely present above the at least one of the source electrode and the drain electrode.

5. The thin-film transistor according to claim 4 ,

wherein the intermediate layer located between the semiconductor layer and the at least one of the source electrode and the drain electrode has a smaller thickness than a thickness of the intermediate layer located between the gate insulating layer and the semiconductor layer.

6. The thin-film transistor according to claim 1 ,

wherein each of the source electrode and the drain electrode includes a first electrode layer that is in contact with the gate insulating layer, and a second electrode layer that is located above the first electrode layer and has a lower injection barrier to the semiconductor layer than an injection barrier to the semiconductor layer of the first electrode layer, and

a distance from a surface of the gate insulating layer to a surface of the semiconductor layer is greater than a thickness of the first electrode layer.

7. The thin-film transistor according to claim 1 ,

wherein each of the source electrode and the drain electrode includes a first electrode layer that is in contact with the gate insulating layer, and a second electrode layer that is located above the first electrode layer and has a lower injection barrier to the semiconductor layer than an injection barrier to the semiconductor layer of the first electrode layer, and

the intermediate layer has a greater thickness than the thickness of the first electrode layer.

8. A display panel comprising a thin-film transistor according to claim 1 .

9. The display panel according to claim 8 , comprising:

a plurality of the thin-film transistors formed in each of a plurality of pixels arranged in a matrix; and

a display element,

wherein one of the thin-film transistors is a driving transistor that drives the display element,

another of the thin-film transistors is a switching transistor that selectively switches driving of the display element, and

the gate insulating layer on which the intermediate layer is formed in the driving transistor has a contact angle against water greater than a contact angle against water of the gate insulating layer on which the intermediate layer is formed in the switching transistor.

10. A method for producing a thin-film transistor comprising:

forming a gate electrode above a substrate;

forming a gate insulating layer that faces the gate electrode;

forming a source electrode and a drain electrode above the gate insulating layer;

forming a partition material layer above the gate insulating layer by applying a partition material having higher liquid repellency than liquid repellency of the gate insulating layer to the gate insulating layer;

discretely forming an intermediate layer above the gate insulating layer and forming a partition having an opening by patterning the partition material layer so that at least a part of the source electrode and the drain electrode is located in the opening, the intermediate layer being made of the same material as a material of the partition material layer; and

forming a semiconductor layer above the intermediate layer within the opening by an application method.

11. The method for producing a thin-film transistor according to claim 10 ,

wherein in the forming of the intermediate layer, the intermediate layer is formed to allow the gate insulating layer on which the intermediate layer is formed to have a contact angle against water smaller than a contact angle against water of the partition.

12. The method for producing a thin-film transistor according to claim 10 ,

wherein in the forming of the intermediate layer, the intermediate layer is formed to allow the gate insulating layer on which the intermediate layer is formed to have a contact angle against water of 40 degrees or more and 70 degrees or less in at least a part of a region of the intermediate layer that is in contact with the semiconductor layer.

13. The method for producing a thin-film transistor according to claim 10 ,

wherein in the forming of the intermediate layer, the intermediate layer is discretely formed above at least one of the source electrode and the drain electrode.

14. The method for producing a thin-film transistor according to claim 10 ,

wherein the forming of the intermediate layer includes exposing the partition material layer to exposure light via a mask, and

in the exposing of the partition material layer, a mask is placed that has a higher transmittance of the exposure light above the partition material layer located on the gate insulating layer than a transmittance of the exposure light above the partition material layer located on the source electrode or the drain electrode.

15. The method for producing a thin-film transistor according to claim 10 ,

wherein in the forming of the intermediate layer, after the intermediate layer has been formed above the gate insulating layer and above at least one of the source electrode and the drain electrode, a thickness of the intermediate layer formed above the at least one of the source electrode and the drain electrode is reduced by irradiating the intermediate layer formed above the at least one of the source electrode and the drain electrode with laser light.

16. The method for producing a thin-film transistor according to claim 10 ,

wherein in the forming of the source electrode and the drain electrode, the source electrode and the drain electrode are formed by forming a first electrode layer that is in contact with the gate insulating layer, and a second electrode layer that is located above the first electrode layer and has a lower injection barrier to the semiconductor layer than the first electrode layer, and

in the forming of the semiconductor layer, the semiconductor layer is formed to make a distance from a surface of the gate insulating layer to a surface of the semiconductor layer greater than a thickness of the first electrode layer.

17. The method for producing a thin-film transistor according to claim 10 ,

wherein in the forming of the source electrode and the drain electrode, the source electrode and the drain electrode are formed by forming a first electrode layer that is in contact with the gate insulating layer, and a second electrode layer that is located above the first electrode layer and has a lower injection barrier to the semiconductor layer than the first electrode layer, and

in the forming of the intermediate layer, the intermediate layer is formed to make a thickness of the intermediate layer greater than a thickness of the first electrode layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2014
From: OKUMOTO, YUKO; MIYAMOTO, AKIHITO
To: PANASONIC CORPORATION
Reel/Frame 032469/0239 →
Priority Claims (1)
JP 2012-131318 · Jun 8, 2012 · national
Continuity (1)
Related Publication 20140159026A1 · Jun 12, 2014