System and method for voltage regulator-gating
A system and method for adaptive activity management of on-chip voltage regulators based upon the workload information is provided to force each on-chip regulator to operate in its most power-efficient load current. In the proposed regulator-gating technique, regulators are adaptively turned ON when the current demand is high and turned OFF when the current demand is low to improve the voltage conversion efficiency. With the proposed regulator-gating system and method, the overall voltage conversion efficiency from the battery or off-chip power supply to the output of the on-chip voltage regulators experiences an approximately 3 times improvement over the prior art techniques.
1. A method for adaptive management of an on-chip distributed power network comprising a plurality of on-chip voltage regulators coupled in parallel to one or more load circuits, the method comprising:
determining the available power budget of the on-chip distributed power network;
monitoring the power consumption of the load circuits;
comparing the available power budget of the on-chip distributed power network to the power consumption of the load circuits and if the power consumption of the load circuits exceeds the available power budget, turning ON one or more of the plurality of on-chip voltage regulators;
sensing, with a voltage sensing circuit of at least one digital low-dropout voltage regulator coupled in parallel with the plurality of on-chip voltage regulators, an output voltage of the on-chip distributed power network;
generating, by the voltage sensing circuit of the at least one digital low-dropout voltage regulator, a gate control voltage in response to a drop in the output voltage of the on-chip distributed power network;
controlling a gate voltage of a pass transistor of the digital low-dropout voltage regulator using the gate control voltage generated by the at least one digital low-dropout voltage regulator;
providing a current, from the pass transistor of the digital low-dropout voltage regulator, to the on-chip distributed power network in response to the drop in output voltage of the on-chip distributed power network; and
turning ON one or more of the plurality of on-chip voltage regulators while the digital low-dropout voltage regulator is providing a current to the on-chip distributed power network.
2. The method of claim 1 , further comprising disabling the current from the pass transistor after the one or more of the plurality of on-chip voltage regulators have been turned ON.