Semiconductor devices and methods of fabricating the same
A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
1. A semiconductor device, comprising:
a lower insulating pattern on a semiconductor substrate;
a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer;
a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern;
an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening; and
a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
2. The device as claimed in claim 1 , wherein the diffusion barrier pattern is formed of silicon oxide, silicon oxynitride, or silicon nitride.
3. The device as claimed in claim 1 , wherein the diffusion barrier pattern has a thickness ranging from about 1 Å to about 15 Å.
4. The device as claimed in claim 1 , wherein the upper gate pattern includes a first upper polysilicon pattern, a barrier metal pattern, and a metal pattern, sequentially stacked on the substrate.
5. The device as claimed in claim 4 , wherein a bottommost surface of the first upper polysilicon pattern is lower than a bottommost surface of the residual insulating pattern.
6. The device as claimed in claim 4 , wherein the upper gate pattern further includes a second upper polysilicon pattern between the residual insulating pattern and the diffusion barrier pattern.
7. The device as claimed in claim 4 , wherein the upper gate pattern further includes a second upper polysilicon pattern between the diffusion barrier pattern and the first upper polysilicon pattern.
8. The device as claimed in claim 7 , wherein a bottommost surface of the first upper polysilicon pattern is higher than a bottommost surface of the residual insulating pattern, and a bottommost surface of the second upper polysilicon pattern is lower than a bottom surface of the residual insulating pattern.
9. The device as claimed in claim 8 , wherein the second upper polysilicon pattern is thicker than the first upper polysilicon pattern.
10. A semiconductor device, comprising:
a cell array region including a plurality of cell gate electrodes, a ground selection electrode, and a string selection electrode; and a peripheral region including a high-voltage gate electrode,
the cell gate electrodes each including:
a tunnel insulating pattern,
a floating gate pattern,
an inter-gate insulating pattern and
a control gate pattern sequentially stacked on a substrate,
the control gate pattern including:
a first polysilicon pattern,
a first diffusion barrier pattern,
a second polysilicon pattern and
a first metal pattern sequentially stacked on the inter-gate insulating pattern, a first barrier metal being interposed between the second polysilicon pattern and the first metal pattern, and
the ground selection electrode, string selection electrode, and high-voltage gate electrode each including:
a lower insulating pattern on the substrate,
a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer,
a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern,
an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and
a second diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
11. The semiconductor device of claim 10 , wherein the first diffusion barrier pattern and the second diffusion barrier pattern are each formed of a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer and each have a thickness ranging from about 1 Å to about 15 Å.
12. The device as claimed in claim 10 , wherein:
the upper gate pattern of the ground selection electrode, string selection electrode, and high-voltage gate electrode includes a first upper polysilicon pattern, a barrier metal pattern, and a metal pattern, sequentially stacked on the substrate.
13. The device as claimed in claim 12 , wherein a bottommost surface of the first upper polysilicon pattern is lower than a bottommost surface of the residual insulating pattern.
14. The device as claimed in claim 12 , wherein:
the upper gate pattern further includes a second upper polysilicon pattern between the diffusion barrier pattern and the first upper polysilicon pattern,
a bottommost surface of the first upper polysilicon pattern is higher than a bottommost surface of the residual insulating pattern, and
a bottommost surface of the second upper polysilicon pattern is lower than a bottom surface of the residual insulating pattern.