Successive approximation analog-to-digital converter (ADC) with dynamic search algorithm

1. A method of an analog-to-digital converter, comprising:

determining, by the analog-to-digital converter, one or more probabilities, each of which corresponds to a probability that an analog input voltage will be in a corresponding one of a plurality of voltage ranges;

selecting, by the analog-to-digital converter, a reference voltage based on the determined one or more probabilities;

comparing, by the analog-to-digital converter, the analog input voltage to the reference voltage to obtain a comparison output;

updating, by the analog-to-digital converter, the reference voltage based on the comparison output; and

repeating, one or more times by the analog-to-digital converter, said comparing and said updating to obtain a digital output code representative of the analog input voltage.

2. The method of claim 1 , wherein the updating the reference voltage is based on the determined one or more probabilities.

3. The method of claim 2 , wherein said selecting comprises setting the reference voltage to ¼ of the full scale voltage of the analog-to-digital converter when the determined one or more probabilities are a first one or more values, and setting the reference voltage to ⅛ of the full scale voltage of the analog-to-digital converter when the determined one or more probabilities are a second one or more values.

4. The method of claim 3 , wherein said selecting comprises setting the reference voltage to ½ of the full scale voltage of the analog-to-digital converter when the determined one or more probabilities are a third one or more values.

5. The method of claim 1 , wherein said updating comprises selecting between a faster back-off process and a slower back-off process of the reference voltage based on the determined one or more probabilities.

6. The method of claim 1 , wherein said updating comprises updating the reference voltage based on an indication of how far above or below the analog input voltage is from the reference voltage.

7. The method of claim 6 , further comprising determining the indication of how far above or below the analog input voltage is from the reference voltage based upon settling behavior of a comparator that is configured to generate the comparison output.

8. The method of claim 6 , wherein said updating comprises selecting between a faster back-off process and a slower back-off process of the reference voltage based on the indication of how far above or below the analog input voltage is from the reference voltage.

9. The method of claim 1 , further comprising outputting a flag signal that indicates whether the digital output code was obtained early or late with respect to a baseline number of comparisons.

10. The method of claim 1 , wherein said selecting is based on peak-to-average power ratio of the analog input voltage.

11. A successive approximation analog-to-digital converter, comprising:

a digital-to-analog converter operable to generate a reference voltage based on a digital reference code;

a comparator operable to compare an analog input voltage to the reference voltage generated by the digital-to-analog converter and generate a comparison output indicative of the comparison; and

a search and decode logic module comprising one or more circuits operable to:

determine one or more probabilities, each of which corresponds to a probability that an analog input voltage will be in a corresponding one of a plurality of voltage ranges;

select the digital reference code based on the determined one or more probabilities;

update the digital reference code based on the comparison output; and

repeat, one or more times, said update of the digital reference code to obtain a digital output code representative of the analog input voltage.

12. The successive approximation analog-to-digital converter of claim 11 , wherein the update of the digital reference code is based on the determined one or more probabilities.

13. The successive approximation analog-to-digital converter of claim 12 , wherein the one or more circuits of the search and decode logic module are further operable to set the digital reference code to a value corresponding to ¼ of the full scale voltage of the analog-to-digital converter when the determined one or more probabilities are a first one or more values, and set the digital reference code to a value corresponding to ⅛ of the full scale voltage of the analog-to-digital converter when the determined one or more probabilities are a second one or more values.

14. The successive approximation analog-to-digital converter of claim 13 , wherein the one or more circuits of the search and decode logic module are further operable to set the digital reference code to a value corresponding to ½ of the full scale voltage of the analog-to-digital converter when the determined one or more probabilities are a third one or more values.

15. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to select between a faster back-off process and a slower back-off process of the reference voltage based on the determined one or more probabilities.

16. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to update the digital reference code based on an indication of how far above or below the analog input voltage is from the reference voltage.

17. The successive approximation analog-to-digital converter of claim 16 , wherein the one or more circuits of the search and decode logic module are further operable to determine how far above or below the analog input voltage is from the reference voltage based upon settling behavior of the comparator.

18. The successive approximation analog-to-digital converter of claim 16 , wherein the one or more circuits of the search and decode logic module are further operable to select between a faster back-off process and a slower back-off process of the reference voltage based on the indication of how far above or below the analog input voltage is from the reference voltage.

19. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to output a flag signal that indicates whether the digital output code was obtained early or late with respect to a baseline number of comparisons.

20. The successive approximation analog-to-digital converter of claim 11 , wherein the one or more circuits of the search and decode logic module are further operable to select the digital reference code based on peak-to-average power ratio of the analog input voltage.