III-nitride enhancement mode transistors with tunable and high gate-source voltage rating

1. A semiconductor device, comprising:

an enhancement mode GaN FET; and

a depletion mode GaN FET;

in which:

a source node of said enhancement mode GaN FET is electrically coupled to a source terminal of said semiconductor device;

a drain node of said enhancement mode GaN FET is electrically coupled to a drain terminal of said semiconductor device;

a gate node of said enhancement mode GaN FET is electrically coupled to a source node of said depletion mode GaN FET;

a gate node of said depletion mode GaN FET is electrically coupled to said source node of said enhancement mode GaN FET; and

a drain node of said depletion mode GaN FET is electrically coupled to a gate terminal of said semiconductor device.

2. The semiconductor device of claim 1 , in which a gate of said enhancement mode GaN FET includes a layer of p-type III-N semiconductor material on a barrier layer on an low-defect layer of gallium nitride.

3. The semiconductor device of claim 2 , in which said gate of said enhancement mode GaN FET includes a layer of metal on said layer of p-type III-N semiconductor material.

4. The semiconductor device of claim 1 , in which a gate of said enhancement mode GaN FET is an insulated gate.

5. The semiconductor device of claim 1 , in which said enhancement mode GaN FET includes a recess in a barrier layer on an low-defect layer of gallium nitride, and a gate of said enhancement mode GaN FET is disposed in said recess.

6. The semiconductor device of claim 1 , in which said enhancement mode GaN FET includes a cap layer of gallium nitride on a barrier layer on an low-defect layer of gallium nitride.

7. The semiconductor device of claim 1 , in which said depletion mode GaN FET includes an low-defect layer of gallium nitride and a barrier layer on said low-defect layer, said barrier layer including a semiconductor material selected from the group consisting of Al x Ga 1-x N and In x Al y Ga 1-x-y N.

8. The semiconductor device of claim 1 , in which said depletion mode GaN FET includes a depletion mode gate of metal.

9. The semiconductor device of claim 1 , in which said depletion mode GaN FET includes a depletion mode gate of III-N semiconductor material.

10. The semiconductor device of claim 1 , in which said depletion mode GaN FET and said enhancement mode GaN FET are formed on a same substrate and same layer structure of III-N semiconductor materials.

11. A process of forming a semiconductor device, comprising the steps of:

forming an enhancement mode GaN FET by a process comprising the steps of:

forming a first low-defect layer comprising gallium nitride over a first substrate;

forming a first barrier layer comprising aluminum gallium nitride over said low-defect layer, so that a two-dimensional electron gas is generated in said first low-defect layer, providing a conductive channel of said enhancement mode GaN FET;

forming a enhancement mode gate over said first barrier layer; and

forming a depletion mode GaN FET by a process comprising the steps of:

forming a second low-defect layer comprising gallium nitride over a second substrate;

forming a second barrier layer comprising aluminum gallium nitride over said second low-defect layer, so that a two-dimensional electron gas is generated in said second low-defect layer providing a conductive channel of said depletion mode GaN FET;

forming a depletion mode gate over said second barrier layer; and

electrically coupling a source node of said enhancement mode GaN FET to a source terminal of said semiconductor device;

electrically coupling a drain node of said enhancement mode GaN FET to a drain terminal of said semiconductor device;

electrically coupling said enhancement mode gate of said enhancement mode GaN FET to a source node of said depletion mode GaN FET;

electrically coupling said depletion mode gate of said depletion mode GaN FET to said source node of said enhancement mode GaN FET; and

electrically coupling a drain node of said depletion mode GaN FET to a gate terminal of said semiconductor device.

12. The process of claim 11 , in which said step of forming said enhancement mode GaN FET includes forming a gate of said enhancement mode GaN FET by forming a layer of p-type III-N semiconductor material on a barrier layer on an low-defect layer of gallium nitride.

13. The process of claim 12 , further including forming a layer of metal on said layer of p-type III-N semiconductor material of said gate of said enhancement mode GaN FET.

14. The process of claim 11 , in which said step of forming said enhancement mode GaN FET includes forming an insulated gate of said enhancement mode GaN FET by forming a metal gate over a gate dielectric layer over a barrier layer on an low-defect layer of gallium nitride.

15. The process of claim 11 , in which said step of forming said enhancement mode GaN FET includes forming a recess in a barrier layer on an low-defect layer of gallium nitride, and forming a gate of said enhancement mode GaN FET in said recess.

16. The process of claim 11 , in which said step of forming said enhancement mode GaN FET includes forming a cap layer of gallium nitride on a barrier layer on an low-defect layer of gallium nitride.

17. The process of claim 11 , in which said step of forming said depletion mode GaN FET includes forming an low-defect layer of gallium nitride and a barrier layer on said low-defect layer, said barrier layer including a semiconductor material selected from the group consisting of Al x Ga 1-x N and In x Al y Ga 1-x-y N.

18. The process of claim 11 , in which said step of forming said depletion mode GaN FET includes forming a depletion mode gate of metal.

19. The process of claim 11 , in which said step of forming said depletion mode GaN FET includes forming a depletion mode gate of III-N semiconductor material.

20. The process of claim 11 , in which said depletion mode GaN FET and said enhancement mode GaN FET are formed on a same substrate and same layer structure of III-N semiconductor materials.