Data storage assembly for archive cold storage
A data storage assembly for cold storage. The data storage assembly includes a circuit board and a plurality of hard disk assemblies (HDA). Each HDA includes a platter and a head assembly to read and write data on the platter. The circuit board includes a processor and a memory. The processor acts as a hard disk controller for the plurality of HDAs and controls the platters. The processor further manages which HDAs are active at a time and the memory is shared by the plurality of HDAs.
1. A data storage assembly comprising:
a circuit board comprising:
a processor;
a memory; and
a read channel; and
a plurality of hard disk assemblies (HDAs), each HDA comprising:
a platter configured to store data; and
a head assembly configured to read data from and write data to the platter;
wherein the processor is configured to be a hard disk controller (HDC) for the plurality of HDAs and manage which of the plurality of HDAs are active at a time, and the plurality of HDAs are configured to share the memory and the read channel among the plurality of HDAs.
2. The data storage assembly of claim 1 , wherein the processor is further configured to determine which one of the plurality of HDAs to utilize for a data command.
3. The data storage assembly of claim 1 , wherein the processor is further configured to perform error recovery for reading and writing to the plurality of HDAs.
4. The data storage assembly of claim 1 , further comprising a motor controller configured to spin the platters of the plurality of HDAs and move the head assemblies of the plurality of HDAs across the respective platters of the plurality of HDAs.
5. The data storage assembly of claim 4 , further comprising a multiplexer connected to the motor controller and configured to communicate with each of the plurality of HDAs.
6. The data storage assembly of claim 1 , further comprising a multiplexer connected to the processor and configured to communicate with each of the plurality of HDAs.
7. The data storage assembly of claim 1 , further comprising a plurality of motor controllers configured to spin the platters and move the head assemblies across the platters of the plurality of HDAs respectively.
8. The data storage assembly of claim 1 , further comprising a sensor configured to detect environmental information of at least one of the plurality of HDAs.
9. The data storage assembly of claim 1 , wherein the processor is further configured to manage power to the plurality of HDAs.
10. The data storage assembly of claim 1 , further comprising a fan configured to cool the plurality of HDAs.
11. The data storage assembly of claim 1 , further comprising a bridge configured to connect the processor to the plurality of HDAs.
12. The data storage assembly of claim 1 , wherein the circuit board further comprises a plurality of connectors for interfacing with the plurality of HDAs.
13. The data storage assembly of claim 1 , wherein each of the plurality of HDAs further comprises a preamp configured to reduce a Signal-to-Noise Ratio (SNR) for data read from the platter.
14. The data storage assembly of claim 1 , further comprising an external data connection, wherein the processor is further configured to interface with the external data connection to share data object manipulation and distributed computing tasks with at least one external processor.
15. The data storage assembly of claim 1 , further comprising a second processor and an external data connection, the second processor connected between the processor and the external data connection such that data object manipulation and distributed computing tasks are shared with at least one external processor.
16. The data storage assembly of claim 1 , wherein the circuit board further comprises a network connection.
17. The data storage assembly of claim 16 , wherein the network connection includes an Ethernet network connection.
18. A hard disk assembly (HDA) comprising:
a platter configured to store data;
a head assembly configured to read data from and write data to the platter;
a preamp configured to reduce a Signal-to-Noise Ratio (SNR) for data read from the platter;
a motor controller configured to move the head assembly across the platter; and
a sensor configured to detect environmental information;
wherein the HDA is configured to communicate with a controller, a read channel shared among a plurality of HDAs, a host interface, and a memory, each external to the IIDA.
19. The HDA of claim 18 , further comprising a processor and a circuit board including the preamp, motor controller, sensor, and a bridge configured to communicate with the processor.
20. The HDA of claim 18 , wherein the platter resides in a helium-filled environment.
21. The HDA of claim 18 , further comprising a processor and a circuit board including a bridge configured to communicate between the preamp, the motor controller, the sensor, and the processor, the read channel, the host interface, and the memory.
22. The HDA of claim 21 , wherein the circuit board further includes a second preamp configured to further reduce a Signal-to-Noise Ratio (SNR) for data read from the platter.
23. The HDA of claim 21 , wherein the circuit board further includes a power large-scale integrated circuit (PLSI) configured to allow hotplugging the HDA.
24. The HDA of claim 21 , wherein the circuit board further includes an emergency power off retract (EPOR) configured to safely power off the HDA.
25. The HDA of claim 18 , wherein the HDA is further configured to communicate with a network via a network connection external to the HDA that is shared among the plurality of HDAs.
26. The HDA of claim 25 , wherein the network connection includes an Ethernet network connection.
27. A data storage assembly comprising:
a circuit board comprising:
a processor; and
a memory; and
a plurality of hard disk assemblies (HDAs), each HDA comprising:
a platter configured to store data;
a head assembly configured to read data from and write data to the platter; and
a power large-scale integrated circuit (PLSI) configured to allow hotplugging the HDA;
wherein the processor is configured to be a hard disk controller (HDC) for the plurality of HDAs and manage which of the plurality of HDAs are active at a time, and the plurality of HDAs are configured to share the memory.
28. The data storage assembly of claim 27 , wherein the circuit board further comprises a network connection.
29. The data storage assembly of claim 28 , wherein the network connection includes an Ethernet network connection.