IP Library Granted Patent US 8,953,072
Granted Patent B2
US 8,953,072 · App. 13/940,963 · Granted Feb 10, 2015

Image taking device and camera system

Inventor: Toshiyuki Nishihara (Kanagawa, JP)
Assignee: Sony Corporation
H04N5/357H04N5/32H04N5/3355H04N5/355
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Quick Facts
Patent No.
US 8,953,072
App. No.
13/940,963
Granted
Feb 10, 2015
Kind
B2
Abstract

An image sensor includes a plurality of pixels, a plurality of sense circuits, and a count circuit. Each sense circuit is configured to read out electrical signals from at least one pixel associated with the sense circuit in order to generate data representing whether or not photons have been received by the sense circuit. The count circuit is in communication with a sense circuit selected from the plurality of sense circuits. The count circuit is configured to provide integration results for the pixels associated with the sense circuits based on the data received from the sense circuits.

Claims (19)

1. A solid-state imaging device comprising:

a pixel section having a plurality of pixels or a plurality of pixel groups including the pixels, each of which has a photoelectric conversion element and outputs a signal generated by the photoelectric conversion element in response to photons;

a sense section having a plurality of sense circuits, each of which makes a binary decision as to whether the photon is input to the photoelectric conversion element during a predetermined period; and

an integration section that stores the binary decision result for each of the pixels or the pixel groups;

wherein,

each of the sense circuits includes at least two capacitors, at least two switches, and at least one amplifier.

2. The solid-state imaging device according to the claim 1 , wherein the reset element resets the pixel or pixel group of each row.

3. The solid-state imaging device according to claim 1 further comprising a count circuit in communication with a sense circuit selected from the plurality of sense circuits and configured to provide integration results for the pixels or pixel groups associated with the sense circuits based on the data received from the sense circuits.

4. The solid-state imaging device according to claim 3 , further comprising a selection circuit to selectively supply data corresponding to the selected sense circuit to the count circuit.

5. The solid-state imaging device according to claim 4 , further comprising a plurality of registers in communication with the selection circuit, each register storing data from a corresponding sense circuit before the data is selectively transferred to the selection circuit.

6. The solid-state imaging device according to claim 5 , wherein the selection circuit sequentially transfers the data from the plurality of registers to the count circuit.

7. The solid-state imaging device according to claim 3 , wherein the plurality of pixels or pixel groups include a set of pixels, the set of pixels being connected to a common signal line that is in communication with a corresponding sense circuit.

8. The solid-state imaging device according to claim 7 , further comprising a reset transistor connected between the common signal line and a reset electric-potential line.

9. The solid-state imaging device according to claim 8 , wherein each pixel includes an internal-amplifier photodiode and a transfer transistor.

10. The solid-state imaging device according to claim 7 , wherein electrical signals from the set of pixels are read out in a cyclical manner by the corresponding sense circuit.

11. The solid-state imaging device according to claim 3 , wherein the data that is generated by the sense circuit is a binary value.

12. The solid-state imaging device of claim 1 , further comprising:

a reset element in each of the pixels or pixel groups to reset the pixel or pixel group in which the photon is not input, and

the reset pixel receives incident light during the predetermined period and readout of the signal from each row of the pixels or pixel groups to the sense section.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040419/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2013
From: NISHIHARA, TOSHIYUKI
To: SONY CORPORATION
Reel/Frame 031188/0223 →
Priority Claims (1)
JP 2009-229893 · Oct 1, 2009 · national
Continuity (2)
Division 12890214 · Sep 24, 2010
Related Publication 20130299677A1 · Nov 14, 2013