Digital semiconductor variable capacitor
A novel semiconductor variable capacitor is presented. The semiconductor structure is simple and is based on a semiconductor variable capacitor with MOS compatible structure suitable for integrated circuits, which has at least three terminals, one of which is used to modulate the capacitance value between the other two terminals of the device, by increasing or decreasing its DC voltage with respect to one of the main terminals of the device. Furthermore, the present invention decouples the AC signal and the DC control voltage preventing distortion of the RF signal. The present invention describes a controllable capacitor whose capacitance value is not necessarily linear with its control voltage, but although possibly abrupt in its characteristic, is utilized to manufacture a semiconductor variable capacitor with digital control to improve its noise and linearity performance while maintaining high quality factor.
1. A digital semiconductor variable capacitor comprising:
a first equivalent capacitance plate;
a second equivalent capacitance plate;
at least one control region formed in a semiconductor region;
wherein said control region forms a rectifying junction with at least a portion of said semiconductor region;
wherein the capacitance value between said first and second capacitance plates of said semiconductor variable capacitor is varied by varying a control voltage;
wherein the variation of said control voltage causes a variation of the voltage drop across said rectifying junction, and
wherein the variation of said capacitance value as a function of said control voltage is substantially digital.
2. The semiconductor variable capacitor of claim 1 , further comprising at least one barrier layer;
wherein said first capacitance plate comprises at least a portion of said semiconductor region;
wherein said second capacitance plate comprises a conductive region covering at least a portion of a surface of said barrier layer, and
wherein said barrier layer is made of one of the materials belonging to the group comprising dielectric and wide band-gap semiconductor materials.
3. The semiconductor variable capacitor of claim 1 , further comprising:
at least one barrier layer;
wherein said first capacitance plate comprises a first and a second highly conductive regions formed in said semiconductor region;
wherein said second capacitance plate comprises a third highly conductive region covering at least a portion of a surface of said barrier layer;
wherein said barrier layer is made of one of the materials belonging to the group comprising dielectric and wide band-gap semiconductor materials, and
wherein each one of said first and second highly conductive regions is directly coupled to at least a portion of said semiconductor region.
4. The semiconductor variable capacitor of claim 1 , further comprising:
at least one barrier layer;
wherein said first capacitance plate comprises:
a first and a second highly conductive regions formed in said semiconductor region;
a third highly conductive region directly coupled to at least one of said first and second highly conductive regions;
wherein said second capacitance plate comprises a fourth highly conductive region covering at least a portion of a surface of said barrier layer;
wherein said barrier layer is made of one of the materials belonging to the group comprising dielectric and wide band-gap semiconductor materials, and
wherein each one of said first and second highly conductive regions is directly coupled to at least a portion of said semiconductor region.
5. A semiconductor variable capacitor according to claim 1 , further comprises:
at least a second, a third, a fourth and a fifth control region formed in said semiconductor region;
a first and a second conductive region forming, respectively, said first and second capacitance plates;
wherein said second control region forms a rectifying junction with said semiconductor region;
wherein each one of said third, fourth and fifth control regions is directly coupled to at least a portion of said semiconductor region.
6. A differential semiconductor variable capacitor comprising at least a first and a second semiconductor variable capacitor according to claim 1 , wherein at least a portion of the first capacitance plate of said first semiconductor variable capacitor is directly coupled to at least a portion of the first capacitance plate of said second semiconductor variable capacitor.
7. A differential semiconductor variable capacitor comprising at least a first and a second semiconductor variable capacitor according to claim 1 ;
wherein the control regions of said first and second semiconductor variable capacitors form, respectively, a first and a second control region of said differential semiconductor variable capacitor, and
wherein the first capacitance plates of said first and said second semiconductor variable capacitors are directly coupled to a third control region of said differential semiconductor variable capacitor.
8. A differential semiconductor variable capacitor comprising at least a first and a second semiconductor variable capacitor according to claim 1 ,
wherein each one of said semiconductor variable capacitors comprises:
a first and a second highly conductive region, each one directly coupled to at least a portion of said semiconductor region;
wherein the control regions of said first and second semiconductor variable capacitors form, respectively, a first and a second control region of said differential semiconductor variable capacitor;
wherein said first highly conductive regions of said first and second semiconductor variable capacitors are placed in physical contact one to each other to form a third control region of said differential semiconductor variable capacitor, and
wherein the second highly conductive regions of said first and second semiconductor variable capacitors form, respectively, a fourth and a fifth control region of said differential semiconductor variable capacitor.
9. A method of operating a semiconductor variable capacitor comprising at least a first control region formed in a semiconductor region, a first equivalent capacitance plate and a second equivalent capacitance plate, the method comprising:
applying a control voltage between at least a portion of said semiconductor region and at least said first control region;
wherein the capacitance value between said first and second capacitance plates of said semiconductor variable capacitor is varied by varying said control voltage;
wherein said first control region forms a rectifying junction with at least a portion of said semiconductor region;
wherein the variation of said control voltage causes a variation of the voltage drop across said rectifying junction, and
wherein the variation of said capacitance value as a function of said control voltage is substantially digital.
10. The method of claim 9 ,
wherein the capacitance value between said first and said second capacitance plates is varied by means of depleting or enhancing at least a portion of said semiconductor region, and
wherein, when said control voltage overcomes a threshold voltage value, the depletion of a portion of said semiconductor material allows the splitting of said semiconductor variable capacitor into two series capacitors.
11. The method of claim 9 ,
wherein said semiconductor variable capacitor further comprises at least one barrier layer;
wherein said first capacitance plate comprises at least a portion of said semiconductor region;
wherein said second capacitance plate comprises a conductive region covering at least a portion of a surface of said barrier layer;
wherein said barrier layer is made of one of the materials belonging to the group comprising dielectric and wide band-gap semiconductor materials, and
wherein the capacitance value between said first and second capacitance plates is varied by depleting or enhancing at least a portion of said semiconductor region.
12. The method of claim 9 ,
wherein said semiconductor variable capacitor further comprises at least one barrier layer;
wherein said first capacitance plate comprises a first and a second highly conductive regions formed in said semiconductor region;
wherein said second capacitance plate comprises a third highly conductive region covering at least a portion of a surface of said barrier layer;
wherein said barrier layer is made of one of the materials belonging to the group comprising dielectric and wide band-gap semiconductor materials;
wherein each one of said first and second highly conductive regions is directly coupled to at least a portion of said semiconductor region, and
wherein the capacitance value between said first and said second equivalent capacitance plates is varied by depleting or enhancing at least a portion of said semiconductor region.
13. The method of claim 9 ,
wherein said semiconductor variable capacitor further comprises:
at least a second and a third control region formed in said semiconductor region;
a first and a second conductive regions forming, respectively, said first and second capacitance plates;
wherein said second control region forms a rectifying junction with said semiconductor region;
wherein said third control region is directly coupled to at least a portion of said semiconductor region, and
wherein said control voltage is applied between said third control region and said first and second control regions.
14. The method of claim 9 ,
wherein said semiconductor variable capacitor further comprises:
at least a second, a third, a fourth, and a fifth control regions formed in said semiconductor region;
at least a first and a second conductive region forming, respectively, said first and second capacitance plates;
wherein said second control region forms a rectifying junction with said semiconductor region;
wherein each one of said third, fourth and fifth control regions is directly coupled to at least a portion of said semiconductor region, and
wherein said control voltage is applied between said third, fourth, and fifth control regions and said first and second control regions.
15. The method of claim 9 ,
wherein said semiconductor variable capacitor further comprises:
at least a second and a third control regions formed in said semiconductor region;
at least a first and a second conductive region forming, respectively, said first and second capacitance plates;
wherein said second control region forms a rectifying junction with said semiconductor region;
wherein said third control region is directly coupled to at least a portion of said semiconductor region, and
wherein each one of said first, second and third control regions is coupled by means of a high impedance component to a bias voltage, and wherein an alternating signal is applied between said first and said second capacitance plates.
16. The method of claim 9 ,
wherein said semiconductor variable capacitor further comprises:
at least a second, a third, a fourth, and a fifth control regions formed in said semiconductor region;
at least a first and a second conductive region forming, respectively, said first and second capacitance plates;
wherein said second control region forms a rectifying junction with said semiconductor region;
wherein each one of said third, fourth and fifth control regions is directly coupled to at least a portion of said semiconductor region, and
wherein each one of said first, second, third, fourth and fifth control regions is coupled through a high impedance component to a bias voltage, and wherein a radio-frequency signal is applied between said first and a second capacitance plates.
17. A method for generating a semiconductor variable capacitor comprising:
forming at least one control region in a semiconductor region;
forming a first equivalent capacitance plate;
forming a second equivalent capacitance plate;
wherein said control region forms a rectifying junction with at least a portion of said semiconductor region;
wherein the capacitance value between said first and second capacitance plates of said semiconductor variable capacitor is varied by varying a control voltage;
wherein the variation of said control voltage causes a variation of the voltage drop across said rectifying junction, and
wherein the variation of said capacitance value as a function of said control voltage is substantially digital.
18. The method of claim 17 , further comprising:
forming a first and a second highly conductive region;
forming at least one barrier layer;
forming said second capacitance plate by means of deposition or epitaxial growth of a third highly conductive region covering at least a portion of a surface of said barrier layer;
wherein said barrier layer is made of one of the materials belonging to the group comprising dielectric and wide band-gap semiconductor materials, and
wherein each one of said first and second highly conductive regions is directly coupled to at least a portion of said semiconductor region.
19. The method of claim 17 , further comprising
forming a first, a second, and a third highly conductive region;
forming at least a second control region is said semiconductor region;
wherein said second control region forms a rectifying junction with at least a portion of said semiconductor region, and
wherein each one of said first, second and third highly conductive regions is directly coupled to at least a portion of said semiconductor region.
20. The method of claim 17 , further comprising:
forming a first, a second, and a third highly conductive region;
forming at least a second control region is said semiconductor region;
forming a first and a second barrier regions;
forming said first capacitance plate by means of deposition or epitaxial growth of a fourth highly conductive region covering at least a portion of a surface of said first barrier region;
forming said second capacitance plate by means of deposition or epitaxial growth of a fifth highly conductive region covering at least a portion of a surface of said second barrier region;
wherein said first and said second barrier regions are made of one of the materials belonging to the group comprising dielectric and wide band-gap semiconductor materials.