IP Library Granted Patent US 8,964,909
Granted Patent B2
US 8,964,909 · App. 13/493,575 · Granted Feb 24, 2015

Maximizing data rate by adjusting codes and code rates

Inventors: John E. Hoffman (Indialantic, FL); George Rodney Nelson, Jr. (Merritt Island, FL); Daniel I. Riley (West Melbourne, FL); Antoine J. Rouphael (Escondito, CA); James A. Proctor, Jr. (Indialantic, FL)
Assignee: Intel Corporation
G11B20/1833H03M13/35H04B1/707H04J13/00H04L1/0003H04L1/0007H04L1/0009H04L1/0025H04L25/14H04L1/1809H04L1/1816H04L2001/0093H04L2001/0096
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,964,909
App. No.
13/493,575
Granted
Feb 24, 2015
Kind
B2
Abstract

The present invention provides for making code rate adjustments and modulation type adjustments in a pseudonoise (PN) encoded CDMA system. Coding rate adjustments may be made by changing the number of information bits per symbol, or Forward Error Code (FEC) coding rate. A forward error correction (FEC) block size is maintained at a constant amount. Therefore, as the number of information bits per symbol are increased, an integer multiple of bits per epoch is always maintained. The scheme permits for a greater flexibility and selection of effective data rates providing information bit rates ranging from, for example, approximately 50 kilobits per second to over 5 mega bits per second (Mbps) in one preferred embodiment.

Claims (23)

1. A subscriber unit comprising:

a forward error correction (FEC) decoder configured to FEC decode a plurality of data blocks, wherein each of the plurality of data blocks is a fixed size and encoded with an error correction code, and to strip redundant FEC code bits from the plurality of data blocks and generate a plurality of decoded segments based on the plurality of data blocks, wherein each of the decoded segments is a variable number of data bits; and

a controller configured to select a decoding rate and to signal the selected decoding rate to the FEC decoder.

2. The subscriber unit of claim 1 , wherein the FEC decoder is configured to decode each of the plurality of data blocks based on the selected decoding rate.

3. The subscriber unit of claim 2 , wherein a size of each of the plurality of decoded segments is based on the selected decoding rate.

4. The subscriber unit of claim 1 , further comprising:

a segment disassembler configured to generate a data frame based on the plurality of decoded segments.

5. The subscriber unit of claim 1 , further comprising:

a demodulator configured to demodulate a received signal and to generate the plurality of data blocks.

6. The subscriber unit of claim 5 , wherein the demodulator is configured to demodulate the received signal using a Quadrature Phase Shift Keying (QPSK) modulation scheme.

7. The subscriber unit of claim 5 , wherein the demodulator is configured to demodulate the received signal using a Quadrature Amplitude Modulation (QAM) modulation scheme.

8. A method for use in a subscriber unit, the method comprising:

forward error correction (FEC) decoding a plurality of data blocks including stripping redundant FEC code bits from the plurality of data blocks, wherein each of the plurality of data blocks is a fixed size and encoded with an error correction code;

generating a plurality of decoded segments based on the plurality of data blocks, wherein each of the plurality of decoded segments is a variable number of data bits; and

selecting a decoding rate, wherein a size of each of the plurality of decoded segments is based on the decoding rate.

9. The method of claim 8 , wherein the decoding is performed based on the selected decoding rate.

10. The method of claim 9 , wherein a size of each of the plurality of decoded segments is based on the selected decoding rate.

11. The method of claim 8 , further comprising:

generating a data frame based on the plurality of decoded segments.

12. The method of claim 8 , further comprising:

demodulating a received signal to produce the plurality of data blocks.

13. The method of claim 12 , wherein the demodulating uses a Quadrature Phase Shift Keying (QPSK) modulation scheme.

14. The method of claim 12 , wherein the demodulating uses Quadrature Amplitude Modulation (QAM) modulation scheme.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2012
From: IPR LICENSING, INC.
To: INTEL CORPORATION
Reel/Frame 029466/0146 →
Continuity (7)
Continuation 12326487 · Dec 2, 2008
Continuation 11633970 · Dec 5, 2006
Continuation 11264847 · Nov 2, 2005
Continuation 09773253 · Jan 31, 2001
Continuation In Part 09447022 · Nov 22, 1999
Continuation In Part 09263358 · Mar 5, 1999
Related Publication 20120250798A1 · Oct 4, 2012