Semiconductor structure and method for manufacturing the same

1. A method for manufacturing a semiconductor structure, comprising:

a) providing a substrate, forming a first semiconductor layer on the substrate, forming a second semiconductor layer on the first semiconductor layer and forming a gate stack on the second semiconductor layer;

b) removing the second semiconductor on both sides of the gate stack to form a first device stack;

c) forming a spacer on both sides of the first device stack, and removing part of the first semiconductor layer on both sides of the first device stack with a certain thickness of the first semiconductor layer left;

d) in a partial area of the first device stack along the width direction, removing the first semiconductor layer located on both sides of the first device stack to expose the substrate;

e) in the partial area of the first device stack along the width direction, forming a supporting isolated structure connected to the substrate under the spacer and under an edge on both sides of the first device stack;

f) removing the remaining first semiconductor layer to form a cavity under the first device stack; and

g) removing the spacer and filling both sides of the first device stack with stressed materials to form a stressed material layer.

2. The method according to claim 1 , wherein the partial area of the first device stack along the width direction comprises two end areas of the first device stack along the width direction.

3. The method according to claim 2 , wherein the second semiconductor layer has a thickness in a range between 10 nm and 30 nm.

4. The method according to claim 2 , wherein the step b) comprises:

etching the second semiconductor layer with the gate stack used as a mask and the first semiconductor layer used as a etch stop layer to form a first base area under the gate stack which, together with the first base area, constitutes the first device stack.

5. The method according to claim 1 , wherein:

the material of the first semiconductor layer is different from that of the substrate and that of the second semiconductor layer.

6. The method according to claim 5 , wherein the second semiconductor layer has a thickness in a range between 10 nm and 30 nm.

7. The method according to claim 5 , wherein the step b) comprises:

etching the second semiconductor layer with the gate stack used as a mask and the first semiconductor layer used as a etch stop layer to form a first base area under the gate stack which, together with the first base area, constitutes the first device stack.

8. The method according to claim 1 , wherein the second semiconductor layer has a thickness in a range between 10 nm and 30 nm.

9. The method according to claim 1 , wherein the step b) comprises:

etching the second semiconductor layer with the gate stack used as a mask and the first semiconductor layer used as a etch stop layer to form a first base area under the gate stack which, together with the first base area, constitutes the first device stack.

10. The method according to claim 9 , wherein the step c) comprises:

forming a stop layer on both sides of the first device stack and forming the spacer on both sides of the stop layer; and

etching the first semiconductor layer located on both sides of the spacer with the first device stack having the spacer used as a mask to remove part of the first semiconductor layer.

11. The method according to claim 10 , wherein the step d) comprises:

forming a lithography mask on the semiconductor structure to cover a partial area of the first device stack along the width direction;

etching the first semiconductor layer with the lithography mask and the first device stack having the spacer used as a mask to expose the substrate; and

removing the lithography mask.

12. The method according to claim 11 , wherein the step e) comprises:

etching back the first semiconductor layer located under the gate stack, wherein the depth of the lateral etching is greater than the total thickness of the spacer and the stop layer;

forming a third semiconductor layer on the upper surface and the side surfaces of the first semiconductor layer by epitaxial growth; and

removing the third semiconductor layer located on the upper surface of the first semiconductor layer by anisotropic etching to form a supporting isolated structure.

13. The method according to claim 1 , wherein:

the level of the upper surface of the stressed material layer is higher than or equal to that of the bottom of the gate stack.

14. A semiconductor structure comprising a substrate, a gate stack, a base area and a source/drain region, wherein the gate stack is located on the base area, the source/drain region is located in the base area, and the base area is located on the substrate, characterized in that:

a supporting isolated structure is provided between the base area and the substrate, wherein part of the supporting structure is connected to the substrate;

a cavity is provided between the base area and the substrate, wherein the cavity is composed of the base area, the substrate and the supporting isolated structure; and

a stressed material layer is provided on both sides of the gate stack, the base area and the supporting isolated structure.

15. The semiconductor structure according to claim 14 , wherein the base area has a thickness in the range between 10 nm and 30 nm.

16. The semiconductor structure according to claim 15 , wherein:

the upper surface of the stressed material layer is higher than or at the same level with the bottom of the gate stack.

17. The semiconductor structure according to claim 14 , wherein:

the upper surface of the stressed material layer is higher than or at the same level with the bottom of the gate stack.