Driver for multi-stage wave guide modulator and method

1. A driver for a number N of electro-optical interface cores each driven by a respective output stage of a multi-stage electro-optical modulator, the driver configured to receive an electrical modulating signal at an input and comprising:

an input impedance matching stage;

a pre-conditioning circuit configured to generate a number M, of delayed replicas of the electrical modulating signal, wherein M is an integer divisor of the number N of cores;

an array of M launch buffers of the replica signals; and

an array of M multi-delay blocks, each multi-delay block comprising a plurality of delay circuits differently cascaded on distinct signal paths, said array of M multi-delay blocks configured to receive, at respective inputs, the M replica signals, and to output N/M differently delayed replicas of the M replica signals, and each driving a corresponding output stage of one on said N electro-optical interface cores.

2. The driver of claim 1 , wherein said plurality of delay circuits is configured to produce a delay of the electrical modulating signal, the delay being equivalent to a one of a fraction of a total optical delay along the multi-stage electro-optical modulator and a multiple thereof with one of the denominator M and a multiple thereof.

3. The driver of claim 1 , wherein said plurality of delay circuits comprises a plurality of programmable delay circuits.

4. The driver of claim 3 , wherein said plurality of programmable delay circuits comprises a plurality of passive ladder filters each having a programmable time constant.

5. The driver of claim 1 , wherein said pre-conditioning circuit comprises programmable delay circuitry configured to compensate for variations based upon process, voltage, and temperature (PVT) spreads.

6. The driver of claim 1 , wherein each respective output stage is adjacent a respectively driven electro-optical interface core.

7. The driver of claim 1 , wherein each respective output stage is at least partly formed within an integrated driver device coupled to respectively driven electrodes of the N electro-optical interface cores.

8. A driver for a number N of electro-optical interface cores, the driver comprising:

a pre-conditioning circuit configured to generate a number M, of delayed replicas of an electrical modulating signal, wherein M is an integer divisor of the number N of cores; and

an array of M multi-delay blocks, each multi-delay block comprising a plurality of delay circuits differently cascaded on distinct signal paths, said array of M multi-delay blocks configured to output N/M differently delayed replicas of the M replica signals.

9. The driver of claim 8 , wherein said plurality of delay circuits is configured to delay the electrical modulating signal, the delay being based upon one of a total optical delay and a multiple thereof with one of the denominator M and a multiple thereof.

10. The driver of claim 8 , wherein said plurality of delay circuits comprises a plurality of programmable delay circuits.

11. The driver of claim 8 , wherein said plurality of programmable delay circuits comprises a plurality of passive ladder filters each having a programmable time constant.

12. The driver of claim 8 , wherein said pre-conditioning circuit comprises programmable delay circuitry configured to compensate for variations based upon process, voltage, and temperature (PVT) spreads.

13. A system comprising:

an optical waveguide;

a number N of electro-optical interface cores distributed along said optical waveguide; and

a driver coupled to the N electro-optical interface cores and comprising

a pre-conditioning circuit configured to generate a number M, of delayed replicas of an electrical modulating signal, wherein M is an integer divisor of the number N of cores, and

an array of M multi-delay blocks, each multi-delay block comprising a plurality of delay circuits differently cascaded on distinct signal paths, said array of M multi-delay blocks configured to output N/M differently delayed replicas of the M replica signals.

14. The system of claim 13 , wherein said plurality of delay circuits is configured to delay the electrical modulating signal, the delay being based upon one of a total optical delay and a multiple thereof with one of the denominator M and a multiple thereof.

15. The system of claim 13 , wherein said plurality of delay circuits comprises a plurality of programmable delay circuits.

16. The system of claim 13 , wherein said plurality of programmable delay circuits comprises a plurality of passive ladder filters each having a programmable time constant.

17. The system of claim 13 , wherein said pre-conditioning circuit comprises programmable delay circuitry configured to compensate for variations based upon process, voltage, and temperature (PVT) spreads.

18. A method of driving a number N of electro-optical interface cores, the method comprising:

generating a number M of delayed replicas of an electrical modulating signal, M being an integer divisor of the number N of cores;

amplifying the M delayed replica signals; and

conveying the amplified replica signals to respective signal path inputs of different combinations of a plurality of delay circuits for generating N/M differently delayed replicas of the amplified replica signals and each driving a corresponding output stage of one on the N electro-optical interface cores.

19. The method of claim 18 , wherein the N/M differently delayed replicas of the electrical modulating signal have delays based upon one of a total optical delay and a multiple thereof with one of the denominator M and a multiple thereof.