Memory and method of operating the same
A memory includes an array of memory cells including a plurality of memory cells with a common source, wherein each of the plurality of memory cells with a common source includes two sub-memory cells, each of the sub-memory cells corresponds to a bit line, and the respective bits are electrically independent. Each of the sub-memory cells in the memory according to the disclosure corresponds to a bit line, and the respective bit lines are electrically independent, thereby effectively avoiding interference to other memory cells which will not be programmed during a program operation.
1. A memory, comprising an array of memory cells including a plurality of memory cells with a common source, wherein each of the plurality of memory cells with a common source includes two sub-memory cells, each of the sub-memory cells corresponds to a bit line, and the respective bit lines are electrically independent, and wherein each sub-memory cell comprises a diffusion area, and two adjacent sub-memory cells of two adjacent memory cells in the direction of a column of the array of memory cells share a diffusion area and a bit line.
2. The memory according to claim 1 , wherein the two sub-memory cells of the memory cell with a common source share a word line.
3. The memory according to claim 2 , wherein the two sub-memory cells of adjacent memory cells with a common source in the direction of a column of the array of memory cells share a bit line.
4. The memory according to claim 2 , wherein two adjacent columns of memory cells with a common source in the direction of a row of the array of memory cells are connected with the bit lines in a mirrored-symmetric way.
5. The memory according to claim 2 , wherein two adjacent columns of memory cells with a common source in the direction of a row of the array of memory cells are connected with the bit lines in the same way.
6. The memory according to claim 2 , further comprising a plurality of common source lines electrically connected with each other.
7. The memory according to claim 2 , further comprising a plurality of common source lines, one of which the two sub-memory cells with a common source share and which are electrically independent of each other.
8. The memory according to claim 2 , comprising a poly-silicon memory, an SONOS memory or a nano-crystal memory.
9. The memory according to claim 1 , wherein two adjacent columns of memory cells with a common source in the direction of a row of the array of memory cells are connected with the bit lines in a mirrored-symmetric way.
10. The memory according to claim 1 , wherein two adjacent columns of memory cells with a common source in the direction of a row of the array of memory cells are connected with the bit lines in the same way.
11. The memory according to claim 1 , further comprising a plurality of common source lines electrically connected with each other.
12. The memory according to claim 1 , further comprising a plurality of common source lines, one of which the two sub-memory cells with a common source share and which are electrically independent of each other.
13. The memory according to claim 1 , comprising a poly-silicon memory, an SONOS memory or a nano-crystal memory.
14. A method of operating a memory, comprising: applying a word line voltage on word lines of two sub-memory cells with a common source; applying a common source line voltage on a common source line; and applying a corresponding bit line voltage or bit line current on two bit lines corresponding to the two sub-memory cells with a common source, wherein the two sub-memory cells with a common source correspond respectively to the two word lines and the two bit lines, and the two word lines are electrically independent of each other and the two bit lines are electrically independent of each other, and wherein during programming of one of the two sub-memory cells with a common source, a supply voltage is applied on the bit line corresponding to the other sub-memory cell.
15. The method of operating a memory according to claim 14 , wherein applying the corresponding bit line voltage or bit line current on the two bit lines corresponding to the two sub-memory cells with a common source comprises: applying the same bit line voltage or the same bit line current concurrently on the two bit lines corresponding to the two sub-memory cells with a common source during programming of the memory.
16. The method of operating a memory according to claim 14 , wherein applying the corresponding bit line voltage or bit line current on the two bit lines corresponding to the two sub-memory cells with a common source comprises: applying the same read voltage or read current concurrently on the bit lines of the sub-memory cells with a common source to concurrently read out data in the sub-memory cells with a common source.
17. A method of operating a memory, comprising: applying a word line voltage on word lines corresponding to two sub-memory cells with a common source; applying a common source line voltage on a common source line; and applying a corresponding bit line voltage or bit line current on two bit lines corresponding to the two sub-memory cells with a common source, wherein the two sub-memory cells with a common source correspond to the two bit lines, and the two bit lines are electrically independent; and the word lines corresponding to the two sub-memory cells with a common source are connected, and wherein during programming of one of the two sub-memory cells with a common source, a supply voltage is applied on the bit line corresponding to the other sub-memory cell.