Resistive random access memory (RRAM) structure and method of making the RRAM structure
The present disclosure provides a resistive random access memory (RRAM) cell. The RRAM cell includes a transistor, a bottom electrode adjacent to a drain region of the transistor and coplanar with the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the drain region.
1. A method of making a logic device having embedded resistive random access memory (RRAM) cells, the method comprising:
forming shallow trench isolation (STI) regions in a semiconductor substrate;
depositing a gate dielectric;
depositing a gate material over the gate dielectric;
patterning the gate dielectric and the gate material into a transistor gate and a bottom electrode, wherein at least a portion of the bottom electrode is disposed over a portion of the STI regions;
forming a source region and a drain region adjacent to the transistor gate;
depositing a first dielectric material layer;
depositing a layer of top electrode material on the first dielectric material layer;
patterning the first dielectric material and the top electrode into a RRAM structure;
depositing an interlayer dielectric (ILD); and
forming a bit line contact through the ILD to the source region and a stretch contact through the ILD to connect the bottom electrode and the drain region.
2. The method of claim 1 , wherein the transistor gate and the bottom electrode comprise polysilicon.
3. The method of claim 1 , further comprising removing the gate material in the transistor gate and depositing one or more different gate materials.
4. The method of claim 1 , wherein the various implanted regions include a source region, a drain region, and a lightly-doped region.
5. The method of claim 4 , further comprising forming a salicide on at least the source region and the drain region.
6. The method of claim 5 , wherein the salicide is formed on the transistor gate and the bottom electrode.
7. The method of claim 1 , further comprising depositing a spacer around the transistor gate and the bottom electrode during implanting regions of the semiconductor substrate operation.
8. The method of claim 1 , wherein:
the top electrode comprises tantalum nitride, titanium nitride or platinum.
9. The method of claim 1 , further comprising forming a source line contact to the top electrode and a word line contact to the transistor gate.
10. The method of claim 1 , wherein the logic device is formed with one more photomask than a logic device without RRAM cells.
11. A method of making a logic device having embedded resistive random access memory (RRAM) cells, the method comprising:
forming a transistor having a gate, a source region, and a drain region;
forming a bottom electrode adjacent to the drain region and having an upper surface coplanar with a top surface of the gate;
depositing a resistive material layer on the bottom electrode;
forming a top electrode on the resistive material layer; and
depositing a conductive material connecting the bottom electrode to the drain region.
12. The method of claim 11 , wherein the conductive material is a stretch contact having no connections to metal layers above the RRAM cell.
13. The method of claim 12 , further comprising:
forming a bit line contact between the source region and a first metal layer, wherein the bit line contact and the stretch contact comprise a same material and thickness.
14. The method of claim 11 , wherein the bottom electrode and the gate comprise a same material and thickness.
15. The method of claim 11 , wherein the bottom electrode and the gate comprise polysilicon.
16. The method of claim 11 , wherein the bottom electrode and the gate comprise aluminum, titanium, titanium nitride, or tantalum nitride.
17. The method of claim 11 , further comprising:
depositing a gate dielectric between the bottom electrode and an underlying substrate.
18. The method of claim 11 , further comprising:
forming shallow trench isolation (STI) regions in the semiconductor substrate; and
forming a doped region in the underlying substrate, wherein the bottom electrode overlies the STI regions and the doped region.
19. The method of claim 11 , wherein the resistive material layer comprises hafnium oxide, zirconium oxide, aluminum oxide, nickel oxide, tantalum oxide or titanium oxide.
20. A method of making a logic device having embedded resistive random access memory (RRAM) cells, the method comprising:
forming a transistor having a gate, a source region, and a drain region;
forming a bottom electrode adjacent to the drain region and coplanar with the gate;
depositing a resistive material layer on the bottom electrode;
forming a top electrode on the resistive material layer; and
depositing a conductive material connecting the bottom electrode to the drain region,
wherein the gate and the bottom electrode comprise a same material.