Dual-band high efficiency Doherty amplifiers with hybrid packaged power devices

1. An amplifying structure, comprising:

a main amplifier configured to amplify a first signal; and

a peak amplifier configured to amplify a second signal,

each of the main amplifier and the peak amplifier including, respectively, a hybrid power device, each of the hybrid power devices including, respectively,

a first power transistor die configured to amplify signals of a first frequency, and

a second power transistor die configured to amplify signals of a second frequency different than the first frequency.

2. The amplifying structure of claim 1 , wherein the amplifying structure is a Doherty amplifier.

3. The amplifying structure of claim 1 , wherein sizes of the first and second power transistor dies of the main amplifier are the same as sizes of the first and second power transistor dies of the peak amplifier, respectively.

4. The amplifying structure of claim 1 , wherein sizes of the first and second power transistor dies of the main amplifier are smaller than sizes of the first and second power transistor dies of the peak amplifier, respectively.

5. The amplifying structure of claim 1 , wherein the first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier each include a laterally diffused metal oxide semiconductor (LDMOS) structure.

6. The amplifying structure of claim 1 , wherein the first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier each include a Gallium Nitride (GaN) structure.

7. The amplifying structure of claim 1 , wherein the first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier each include one or more high heterojunction bipolar transistors (HBT).

8. The amplifying structure of claim 1 , wherein the first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier each include one or more pseudomorphic heterojunction pHEMT power transistors.

9. The amplifying structure of claim 1 , wherein the second frequency is higher than the first frequency, the first power transistor dies of the main amplifier and the peak amplifier each include a laterally diffused metal oxide semiconductor (LDMOS) structure, and the second power transistor dies of the main amplifier and the peak amplifier each include a Gallium Nitride (GaN) structure.

10. The amplifying structure of claim 1 , wherein a difference between the first frequency and the second frequency is in between 200 MHz and 1000 MHz.

11. The amplifying structure of claim 1 , wherein a difference between the first frequency and the second frequency is more than 1000 MHz.

12. The amplifying structure of claim 1 wherein,

the hybrid power device of the main amplifier includes a first input internal matching network configured to operate at the first frequency, the first input internal matching network including a first capacitor and being configured to transform an input impedance of the first power transistor die of the hybrid device of the main amplifier, and

the hybrid power device of the main amplifier includes a second input internal matching network configured to operate at the second frequency, the second input internal matching network including a second capacitor and being configured to transform an input impedance of the second power transistor die of the hybrid device of the main amplifier.

13. The amplifying structure of claim 12 wherein,

the first input internal matching network includes a first plurality of inner bonding wires connecting the first capacitor to the first power transistor die of the hybrid device of the main amplifier and a first plurality of outer bonding wires connecting the first capacitor to a first gate lead, and

the second input internal matching network includes a second plurality of inner bonding wires connecting the second capacitor to the second power transistor die of the hybrid device of the main amplifier and a second plurality of outer bonding wires connecting the second capacitor to a second gate lead.

14. The amplifying structure of claim 1 wherein,

the hybrid power device of the main amplifier includes a first output internal matching network configured to operate at the first frequency, the first output internal matching network including a first capacitor and being configured to transform an output impedance of the first power transistor die of the hybrid device of the main amplifier, and

the hybrid power device of the main amplifier includes a second output internal matching network configured to operate at the second frequency, the second output internal matching network including a second capacitor and being configured to transform an output impedance of the second power transistor die of the hybrid device of the main amplifier.

15. The amplifying structure of claim 14 wherein,

the first output internal matching network includes a first plurality of inner bonding wires connecting the first capacitor to the first power transistor die of the hybrid device of the main amplifier and a first plurality of outer bonding wires connecting the first capacitor to a first drain lead, and

the second output internal matching network includes a second plurality of inner bonding wires connecting the second capacitor to the second power transistor die of the hybrid device of the main amplifier and a second plurality of outer bonding wires connecting the second capacitor to a second drain lead.

16. The amplifying structure of claim 1 wherein,

the hybrid power device of the peak amplifier includes a first input internal matching network configured to operate at the first frequency, the first input internal matching network including a first capacitor and being configured to transform an input impedance of the first power transistor die of the hybrid device of the peak amplifier, and

the hybrid power device of the peak amplifier includes a second input internal matching network configured to operate at the second frequency, the second input internal matching network including a second capacitor and being configured to transform an input impedance of the second power transistor die of the hybrid device of the peak amplifier.

17. The amplifying structure of claim 16 wherein,

the first input internal matching network includes a first plurality of inner bonding wires connecting the first capacitor to the first power transistor die of the hybrid device of the peak amplifier and a first plurality of outer bonding wires connecting the first capacitor to a first gate lead, and

the second input internal matching network includes a second plurality of inner bonding wires connecting the second capacitor to the second power transistor die of the hybrid device of the peak amplifier and a second plurality of outer bonding wires connecting the second capacitor to a second gate lead.

18. The amplifying structure of claim 1 wherein,

the hybrid power device of the peak amplifier includes a first output internal matching network configured to operate at the first frequency, the first output internal matching network including a first capacitor and being configured to transform an output impedance of the first power transistor die of the hybrid device of the peak amplifier, and

the hybrid power device of the peak amplifier includes a second output internal matching network configured to operate at the second frequency, the second output internal matching network including a second capacitor and being configured to transform an output impedance of the second power transistor die of the hybrid device of the peak amplifier.

19. The amplifying structure of claim 18 wherein,

the first output internal matching network includes a first plurality of inner bonding wires connecting the first capacitor to the first power transistor die of the hybrid device of the peak amplifier and a first plurality of outer bonding wires connecting the first capacitor to a first drain lead, and

the second output internal matching network includes a second plurality of inner bonding wires connecting the second capacitor to the second power transistor die of the hybrid device of the peak amplifier and a second plurality of outer bonding wires connecting the second capacitor to a second drain lead.

20. The amplifying structure of claim 1 , wherein one or more of the hybrid device of the main amplifier and the hybrid device of the peak amplifier include one or more low-temperature co-fired creaming (LTCC) integrated circuits for implementing integrated input and output matching networks with both or either of the main and the peak hybrid power devices.