IP Library Granted Patent US 9,041,221
Granted Patent B2
US 9,041,221 · App. 13/993,714 · Granted May 26, 2015

Electronic component implementing structure intermediate body, electronic component implementing structure body and manufacturing method of electronic component implementing structure body

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Quick Facts
Patent No.
US 9,041,221
App. No.
13/993,714
Granted
May 26, 2015
Kind
B2
Abstract

An implementing structure intermediate body including: a first chip having a first connection terminal; a second chip having a second connection terminal in a face that faces the first chip; and a film wiring substrate having a third connection terminal in one face, which is arranged between the first chip and the second chip, is loaded on a chip loading substrate having a fifth connection terminal so that another one face of the first chip is confronted thereby. In the film wiring substrate, there is a portion that is located outside any of the first chip and the second chip, at the tip part, is provided a fourth connection terminal connected to the third connection terminal by wiring, one part of the first connection terminal is connected with the second connection terminal, the third connection terminal is connected with another one part of the first connection terminal, and the fifth connection terminal is connected to the fourth connection terminal.

Claims (31)

1. An electronic component implementing structure body, comprising:

an electronic component implementing structure intermediate body; and a chip loading substrate, wherein the electronic component implementing structure intermediate body comprises:

a first semiconductor chip that has a first connection terminal on one face;

a second semiconductor chip that has a second connection terminal on a face which faces the one face of the first semiconductor chip; and

a film wiring substrate that is allowed to be divided into 4 pieces, has flexibility, has a third connection terminal at least on one face, and is arranged between the first semiconductor chip and the second semiconductor chip,

at least one part of the first connection terminal is connected with at least one part of the second connection terminal,

the third connection terminal is connected at least with either of another one part of the first connection terminal and another one part of the second connection terminal,

on the film wiring substrate, there is a portion that is located outside any end parts of the first semiconductor chip and the second semiconductor chip,

at a tip part of the portion, is provided a fourth connection terminal that is connected to the third connection terminal by wiring,

the chip loading substrate has a fifth connection terminal, on which the electronic component implementing structure intermediate body is loaded so that another one face of the first semiconductor chip is confronted by the chip loading substrate,

the fifth connection terminal is connected to the fourth connection terminal of the film wiring substrate, and

the film wiring substrate is curved between the third connection terminal and the fifth connection terminal.

2. An electronic component implementing structure body according to claim 1 , wherein

on the film wiring substrate, is provided a hole part, and

the at least one part of the first connection terminal, and the at least one part of the second connection terminal are connected via the hole part.

3. An electronic component implementing structure body according to claim 1 , wherein

on at least one spot of an outer fringe part of the film wiring substrate, there is a notch.

4. An electronic component implementing structure body according to claim 1 , wherein

the first semiconductor chip and the second semiconductor chip are arranged so as to be opposing, and a difference in length between each correspondingly opposing side of the first semiconductor chip and the second semiconductor chip is within ±5%.

5. A manufacturing method of an electronic component implementing structure body, comprising:

a semiconductor chip loading step of loading, onto a chip loading substrate, a first semiconductor chip with a first connection terminal formed on one face so that a face on which the first connection terminal is not formed is confronted by the chip loading substrate;

a first terminal connecting step of electrically connecting one part of the first connection terminal of the first semiconductor chip, and a third connection terminal formed on one face of a film wiring substrate that is allowed to be divided into 4 pieces;

a second terminal connecting step of, from a side where connection of the film wiring substrate of the first semiconductor chip has been carried out, overlaying and laminating a second semiconductor chip with a second connection terminal formed on one face, and then electrically connecting a first connection terminal that is not connected to the third connection terminal, and the second connection terminal; and

a third terminal connecting step of electrically connecting, to a fifth connection terminal that is formed on the chip loading substrate, a fourth connection terminal that is connected to the third connection terminal and is formed at a tip portion of a portion of the film wiring substrate, the portion being located outside any end parts of the first semiconductor chip and the second semiconductor chip, wherein

the film wiring substrate is curved between the third connection terminal and the fifth connection terminal.

6. A manufacturing method of an electronic component implementing structure body according to claim 5 , wherein

processing of the first terminal connecting step, the second terminal connecting step, the semiconductor chip loading step, and the third terminal connecting step are carried out in that order.

7. A manufacturing method of an electronic component implementing structure body according to claim 5 , wherein

processing of the first terminal connecting step, the semiconductor chip loading step, the third terminal connecting step, and the second terminal connecting step are carried out in that order.

8. A manufacturing method of an electronic component implementing structure body according to claim 5 , wherein

processing of the semiconductor chip loading step, the first terminal connecting step, the second terminal connecting step, and the third terminal connecting step are carried out in that order.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2013
From: OCHI, SHOZO; USHIROKAWA, KAZUYA; KUSUMOTO, KEIICHI; YAMADA, TAKASHI; YASUE, KEN
To: PANASONIC CORPORATION
Reel/Frame 030801/0078 →