IP Library Granted Patent US 9,043,572
Granted Patent B2
US 9,043,572 · App. 13/550,141 · Granted May 26, 2015

Automatically preventing large block writes from starving small block writes in a storage device

Inventors: Michael T. Benhase (Tucson, AZ); Andrew D. Walls (San Jose, CA)
Assignee: International Business Machines Corporation
G06F3/00G06F3/0608G06F12/023G06F13/00
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Quick Facts
Patent No.
US 9,043,572
App. No.
13/550,141
Granted
May 26, 2015
Kind
B2
Abstract

A mechanism is provided in a storage device for performing a write operation. The mechanism configures a write buffer memory with a plurality of write buffer portions. Each write buffer portion is dedicated to a predetermined block size category within a plurality of block size categories. For each write operation from an initiator, the mechanism determines a block size category of the write operation. The mechanism performs each write operation by writing to a write buffer portion within the plurality of write buffer portions corresponding to the block size category of the write operation.

Claims (69)

1. A computer program product comprising a non-transitory computer readable medium having a computer readable program stored therein, wherein the computer readable program, when executed on a processor of a storage device, causes the processor to:

configure a write buffer memory with a plurality of write buffer portions, wherein each write butler portion is dedicated to a predetermined block size category within a plurality of block size categories;

for each write operation from an initiator, determine a block size category of the write operation;

perform each write operation by writing to a write buffer portion within the plurality of write buffer portions corresponding to the block size category of the write operation; and

responsive to a write buffer portion corresponding to a block size category of a given write operation being full, update a blocking delay value for the block size category of the given write operation.

2. The computer program product of claim 1 , wherein the computer readable program further causes the processor to:

adjust sizes of the plurality of write buffer portions based on blocking delay values of the block size categories.

3. The computer program product of claim 1 , wherein configuring the write buffer memory comprises configuring a shared buffer portion, wherein the shared buffer portion stores writes of all block size categories, wherein the computer readable program further causes the processor to:

responsive to a write buffer portion corresponding to a block size category of a given write operation being full, perform the given write operation by writing to the shared buffer portion.

4. The computer program product of claim 3 , wherein the computer readable program further causes the processor to:

responsive to the shared buffer portion being full, update a blocking delay value for the block size category of the given write operation.

5. The computer program product of claim 3 , wherein the computer readable program further causes the processor to:

for each write operation from the initiator, increment a counter corresponding to the block size category of the write operation;

responsive to expiration of a time interval, determine whether a given counter corresponding to a given block size category is less than a predetermined threshold; and

responsive to the given counter being less than the predetermined threshold, convert the write buffer portion corresponding to the given block size category to a shared buffer portion.

6. The computer program product of claim 5 , wherein the computer readable program further causes the processor to:

restart the time interval;

for each write operation from the initiator, increment a counter corresponding to the block size category of the write operation;

responsive to expiration of the time interval, determine whether the given counter is greater than the predetermined threshold; and

responsive to the given counter being greater than the predetermined threshold, reconfigure the write buffer portion corresponding to the given block size.

7. The computer program product of claim 1 , wherein the computer readable program further causes the processor to:

determine a bandwidth percentage for a first block size category;

complete writes of only the first block size category until the bandwidth percentage is reached; and

complete a write of the second block size category responsive to the bandwidth percentage being reached.

8. The computer program product of claim 1 , wherein the computer readable program is stored in a computer readable storage medium in a data processing system and wherein the computer readable program was downloaded over a network from a remote data processing system.

9. The computer program product of claim 1 , wherein the computer readable program is stored in a computer readable storage medium in a server data processing system and wherein the computer readable program is downloaded over a network to a remote data processing system for use in a computer readable storage medium with the remote system.

10. A method, in a storage device, for performing a write operation, the method comprising:

configuring a write buffer memory with a plurality of write buffer portions, wherein each write buffer portion is dedicated to a predetermined block size category within a plurality of block size categories;

for each write operation from an initiator, determining a block size category of the write operation;

performing each write operation by writing to a write buffer portion within the plurality of write buffer portions corresponding to the block size category of the write operation; and

responsive to a write buffer portion corresponding to a block size category of a given write operation being full, updating a blocking delay value for the block size category of the given write operation.

11. The method of claim 10 , further comprising:

adjusting sizes of the plurality of write buffer portions based on blocking delay values of the block size categories.

12. The method of claim 10 , wherein configuring the write buffer memory comprises configuring a shared buffer portion, wherein the shared buffer portion stores writes of all block size categories, the method further comprising:

responsive to a write buffer portion corresponding to a block size category of a given write operation being full, performing the given write operation by writing to the shared buffer portion.

13. The method of claim 12 , further comprising:

responsive to the shared buffer portion being full, updating a blocking delay value for the block size category of the given write operation.

14. The method of claim 12 , further comprising:

for each write operation from the initiator, incrementing a counter corresponding to the block size category of the write operation;

responsive to expiration of a time interval, determining whether a given counter corresponding to a given block size category is less than a predetermined threshold; and

responsive to the given counter being less than the predetermined threshold, convening the write buffer portion corresponding to the given block size category to a shared buffer portion.

15. The method of claim 14 , further comprising:

restarting the time interval;

for each write operation from the initiator, incrementing a counter corresponding to the block size category of the write operation;

responsive to expiration of the time interval, determining whether the given counter is greater than the predetermined threshold; and

responsive to the given counter being greater than the predetermined threshold, reconfiguring the write buffer portion corresponding to the given block size.

16. The method of claim 10 , further comprising:

determining a bandwidth percentage for a first block size category;

completing writes of only the first block size category until the bandwidth percentage is reached; and

completing a write of the second block size category responsive to the bandwidth percentage being reached.

17. An apparatus, comprising:

a processor; and

a non-transitory memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to:

configure a write buffer memory with a plurality of write buffer portions, wherein each write buffer portion is dedicated to a predetermined block size category within a plurality of block size categories;

for each write operation from an initiator, determine a block size category of the write operation;

perform each write operation by writing to a write buffer portion within the plurality of write buffer portions corresponding to the block size category of the write operation; and

responsive to a write buffer portion corresponding to a block size category of a given write operation being full, update a blocking delay value for the block size category of the given write operation.

18. The apparatus of claim 17 , wherein the instructions further cause the processor to:

adjust sizes of the plurality of write buffer portions based on blocking delay values of the block size categories.

19. The apparatus of claim 17 , wherein configuring the write buffer memory comprises configuring a shared buffer portion, wherein the shared buffer portion stores writes of all block size categories, wherein the instructions further cause the processor to:

responsive to a write buffer portion corresponding to a block size category of a given write operation being full, perform the given write operation by writing to the shared buffer portion;

responsive to the shared buffer portion being full, update a blocking delay value for the block size category of the given write operation;

for each write operation from the initiator, increment a counter corresponding to the block size category of the write operation;

responsive to expiration of a time interval, determine whether a given counter corresponding to a given block size category is less than a predetermined threshold; and

responsive to the given counter being less than the predetermined threshold, convert the write buffer portion corresponding to the given block size category to a shared buffer portion.

20. The apparatus of claim 17 , wherein the instructions further cause the processor to:

determine a bandwidth percentage for a first block size category;

complete writes of only the first block size category until the bandwidth percentage is reached; and

complete a write of the second block size category responsive to the bandwidth percentage being reached.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2012
From: BENHASE, MICHAEL T.; WALLS, ANDREW D.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 028563/0474 →
Continuity (1)
Related Publication 20140019707A1 · Jan 16, 2014