Thin film transistor array panel and liquid crystal display device including the same

1. A thin film transistor array panel, comprising:

a first substrate;

a gate line and a data line on the first substrate;

a storage electrode line on the first substrate, wherein a constant voltage is applied thereto;

a first thin film transistor which is connected to the gate line and the data line, and comprises a first gate electrode, a first source electrode and a first drain electrode;

a second thin film transistor which is connected to the gate line and the data line, and comprises a second gate electrode, a second source electrode and a second drain electrode;

a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line, and comprises a third gate electrode, a third source electrode and a third drain electrode;

an extension electrode which extends from the third gate electrode and overlaps the first drain electrode;

a first subpixel electrode which is connected to the first thin film transistor; and

a second subpixel electrode which is connected to the second thin film transistor,

wherein the third source electrode of the third thin film transistor is directly connected to the second drain electrode of the second thin film transistor.

2. The thin film transistor array panel of claim 1 , further comprising:

an auxiliary electrode which protrudes from the storage electrode line;

wherein

the first gate electrode and the second gate electrode protrude from the gate line and are connected to each other,

the first source electrode protrudes from the data line and overlaps the first gate electrode, and the first drain electrode is spaced apart from the first source electrode,

the second source electrode is connected to the first source electrode and overlaps the second gate electrode, and the second drain electrode includes the drain electrode of the second thin film transistor which is spaced apart from the second source electrode,

the third gate electrode protrudes from the gate line in a same direction as the first gate electrode and the second gate electrode, and is spaced apart from the second gate electrode,

the third source electrode includes the source electrode of the third thin film transistor which is connected to the second drain electrode and overlaps the third gate electrode, and

the third drain electrode is spaced apart from the third source electrode and overlaps the third gate electrode and the auxiliary electrode.

3. The thin film transistor array panel of claim 2 , further comprising:

a connection electrode which connects the third drain electrode and the auxiliary electrode to each other.

4. The thin film transistor array panel of claim 2 , wherein:

the second drain electrode and the third source electrode are between the second gate electrode and the third gate electrode which are spaced apart from each other.

5. The thin film transistor array panel of claim 4 , wherein:

the first source electrode and the second source electrode are curved in a ‘C’ shape.

6. The thin film transistor array panel of claim 5 , wherein:

the first drain electrode and the second drain electrode each include:

a first portion having a rod shape; and

a second portion which is connected to the first portion and is wider than the first portion,

the first portion of first drain electrode is enclosed by the first source electrode,

the first portion of the second drain electrode is enclosed by the second source electrode, and

the first portion of the second drain electrode is connected to the third source electrode via the second portion of the second drain electrode.

7. The thin film transistor array panel of claim 6 , further comprising:

a gate insulating layer on the gate line, the first gate electrode, the second gate electrode and the third gate electrode; and

a passivation layer on the first, second and third source electrodes and on the first, second and third drain electrodes.

8. The thin film transistor array panel of claim 7 , wherein

the passivation layer comprises:

a first contact hole which exposes a portion of the first drain electrode; and

a second contact hole which exposes a portion of the second drain electrode; and

the passivation layer and the gate insulating layer comprise a third contact hole which exposes a portion of the third drain electrode and a portion of the auxiliary electrode.

9. The thin film transistor array panel of claim 8 , further comprising:

a connection electrode which is connected to the third drain electrode and the auxiliary electrode through the third contact hole,

wherein

the first subpixel electrode is connected to the first drain electrode through the first contact hole, and

the second subpixel electrode is connected to the second drain electrode through the second contact hole.

10. The thin film transistor array panel of claim 9 , wherein:

the portion of the auxiliary electrode exposed by the third contact hole does not overlap the third drain electrode.

11. The thin film transistor array panel of claim 9 , wherein:

the connection electrode includes a same material, and is in a same layer as the first subpixel electrode and the second subpixel electrode.

12. The thin film transistor array panel of claim 4 , wherein

the extension electrode is spaced apart from the first gate electrode.

13. The thin film transistor array panel of claim 12 , wherein:

the first drain electrode includes:

a first portion which has a rod shape, is enclosed by the first source electrode and overlaps the first gate electrode;

a second portion which is connected to the first portion, is wider than the first portion and is between the first gate electrode and the extension electrode; and

a third portion which is connected to the second portion, has a rod shape, is narrower than the second portion and overlaps the extension electrode.

14. The thin film transistor array panel of claim 3 , further comprising:

a dummy line which overlaps the data line.

15. The thin film transistor array panel of claim 14 , wherein:

the dummy line is connected to the storage electrode line.

16. The thin film transistor array panel of claim 14 , wherein:

the dummy line is connected to the connection electrode.

17. The thin film transistor array panel of claim 16 , wherein:

the dummy line includes a same material and is in a same layer as the connection electrode, the first subpixel electrode and the second subpixel electrode.

18. A liquid crystal display, comprising:

a first substrate and a second substrate;

a liquid crystal layer between the first substrate and the second substrate;

a gate line, a data line and a storage electrode line on the first substrate;

a first thin film transistor which is connected with the gate line and the data line, and comprises a first gate electrode, a first source electrode and a first drain electrode;

a second thin film transistor which is connected to the gate line and the data line, and comprises a second gate electrode, a second source electrode and second drain electrode;

a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line, and comprises a third gate electrode, a third source electrode and a third drain electrode;

an extension electrode which extends from the third gate electrode and overlap the first drain electrode;

a first subpixel electrode which is connected to the first thin film transistor;

a second subpixel electrode which is connected to the second thin film transistor; and

a common electrode on the second substrate, wherein the common electrode forms an electric field with the first subpixel electrode and the second subpixel electrode,

wherein the third source electrode of the third thin film transistor is directly connected to the second drain electrode of the second thin film transistor.

19. The liquid crystal display of claim 18 , further comprising:

an auxiliary electrode which protrudes from the storage electrode line;

wherein

the first gate electrode and the second gate electrode protrude from the gate line and are connected to each other,

the first source electrode protrudes from the data line and overlaps the first gate electrode, and the first drain electrode is spaced apart from the first source electrode; and

the second source electrode is connected to the first source electrode and overlaps the second gate electrode, and the second drain electrode includes the drain electrode of the second thin film transistor which is spaced apart from the second source electrode,

the third gate electrode protrudes from the gate line in a same direction as the first gate electrode and the second gate electrode, and is spaced apart from the second gate electrode,

the third source electrode includes the source electrode of the third thin film transistor which is connected to the second drain electrode and overlaps the third gate electrode, and

the third drain electrode is spaced apart from the third source electrode and overlaps the third gate electrode and the auxiliary electrode.

20. The liquid crystal display of claim 19 , further comprising:

a connection electrode which connects the third drain electrode and the auxiliary electrode to each other,

wherein the second drain electrode and the third source electrode are between the second gate electrode and the third gate electrode which are spaced apart from each other.