Hardware for performing arithmetic operations

1. Hardware for performing arithmetic operations on a compressed matrix format stored in memory, the compressed matrix format comprising a bitmap denoting whether individual entries within the matrix are zero or not, the hardware comprising:

a scheduler operable to generate a schedule of instructions from the bitmap denoting whether an entry in the matrix is zero or not, and

an arithmetic circuit configured to perform arithmetic operations on the matrix using non-zero values in accordance with the generated schedule.

2. Hardware according to claim 1 , wherein the arithmetic circuit is a Single Instruction Multiple Data (SIMD) floating point unit.

3. Hardware as claimed in claim 1 , further comprising a software interface configured for receiving the bitmap.

4. Hardware as claimed in claim 3 , wherein the software interface is operable to read the number of bitmap-blocked tiles in the matrix.

5. Hardware as claimed in claim 3 , wherein the software interface is operable to read the number of rows in the matrix.

6. Hardware as claimed in claim 5 , wherein the software interface is operable to read the number of columns in the matrix.

7. Hardware as claimed in claim 3 , wherein the software interface is operable to read the number of non-zero entries in the matrix.

8. Hardware as claimed in claim 3 , wherein the software interface is operable to read the number of rows in a block tile of the matrix.

9. Hardware as claimed in claim 3 , wherein the software interface is operable to read the number of columns in a block tile of the matrix.

10. Hardware as claimed in claim 3 , wherein the software interface is operable to read a base address of a first array containing the nonzero data elements of the matrix.

11. Hardware as claimed in claim 10 , wherein the software interface is operable to read a base address of a second array which holds the row entries containing non-zero tiles.

12. Hardware as claimed in claim 11 , wherein the software interface is operable to read a base address of a third array which contains the column addresses of the non-zero tiles.

13. Hardware as claimed in claim 12 , wherein the software interface is operable to read a base address of a fourth array which holds the bitmap.

14. Hardware as claimed in claim 13 , wherein the first, second, third and fourth arrays are stored in external memory.

15. Hardware as claimed in claim 3 , further comprising registers for storing data received via the software interface.

16. Hardware as claimed in claim 15 , further comprising a mapped memory interface for facilitating writing data received through the software interface into the registers.

17. Hardware as claimed in claim 16 , where the registers store a memory map.

18. Hardware as claimed in claim 15 , wherein the registers store commands for implementing sparse-matrix vector products (SMVM).

19. Hardware as claimed in claim 18 , wherein the commands includes a command to initiate SMVM.

20. Hardware as claimed in claim 18 , wherein the commands includes a command to pause an SMVM calculation.

21. Hardware as claimed in claim 20 , wherein the commands includes a command to cause a paused SMVM calculation to be resumed.

22. Hardware as claimed in claim 20 , wherein the commands includes a command to cause a paused SMVM calculation to be terminated.

23. Hardware as claimed in claim 18 , wherein the commands includes a command to reset registers.

24. Hardware as claimed in claim 18 , wherein the commands includes a stop command.

25. Hardware as claimed in claim 1 , wherein the scheduler is configured to generates a list of non-zero partial-products to be evaluated along with the relative column and row addresses derived from the bitmap.

26. Hardware as claimed in claim 25 , wherein the schedule generated by the scheduler is compressed according to a bitmap.

27. Hardware as claimed in claim 1 , wherein the scheduler comprises an array of multiplexers.

28. Hardware as claimed in claim 1 , wherein the scheduler comprises multiple bit-slices.

29. Hardware as claimed in claim 28 , wherein the multiplexers have associated Look-Up Tables (LUTs).

30. Hardware as claimed in claim 1 , wherein the scheduler forms part of a programmable processor.

31. Hardware as claimed in claim 1 , wherein the scheduler further comprises an iteration-counter operable to determine the number of arithmetic iterations required.

32. Hardware as claimed in claim 31 , wherein the iteration-counter comprises a plurality of full adders.

33. Hardware as claimed in claim 32 , wherein the iteration-counter further comprises an OR gate.

34. Hardware as claimed in claim 1 , further comprising a controller configured for generating control signals.

35. Hardware as claimed in claim 34 , wherein the controller is configured for applying the control signals to the arithmetic circuit for controlling arithmetic operations.

36. Hardware as claimed in claim 35 , wherein the controls signals include a signal for loading y-vector entries.

37. Hardware as claimed in claim 35 , wherein the control signals includes a signal for loading a bitmap.

38. Hardware as claimed in claim 35 , wherein the control signals includes a signal for generating a schedule.

39. Hardware as claimed in claim 35 , wherein the control signals includes a signal for loading x-vector entries.

40. Hardware as claimed in claim 39 , wherein the control signals includes a signal for reading matrix entries from memory.

41. Hardware as claimed in claim 40 , wherein the control signals includes a signal for selecting the correct x vector entries to be multiplied by each matrix entry.

42. Hardware as claimed in claim 41 , wherein the control signals include a signal for evaluating a partial product.

43. Hardware as claimed in claim 42 , wherein the control signals include a signal for evaluating arithmetic.

44. Hardware as claimed in claim 42 , wherein the control signals include a signal for selecting the correct y value to be updated.

45. Hardware as claimed in claim 44 , wherein the control signals include a signal for writing contents to external memory.

46. Hardware as claimed in claim 35 , wherein the controller is configured for detecting data-dependencies which can lead to data hazards.

47. Hardware as claimed in claim 46 , wherein the controller is configured to stall a datapath until the data-dependencies have been resolved.

48. Hardware as claimed in claim 35 , wherein the controller is operable to pause an operation in order to wait for data from an external bus, data-cache or external SDRAM.

49. Hardware as claimed in claim 1 , wherein the scheduler is configured to perform look-ahead in order to resolve dependencies.

50. Hardware as claimed in claim 28 , wherein the row and column address look-up tables (LUTs) used by the scheduler to generate addresses used in the schedule are programmable.

51. Hardware as claimed in claim 1 , wherein the number of rows and columns decoded from the bitmap are programmable.

52. Hardware as claimed in claim 1 , where the bitmap can be used to generate a list of logical and/or arithmetic instructions and array references for operations other than sparse-matrix vector products.

53. A hardware assembly comprising the hardware as claimed in claim 1 .

54. A hardware assembly as claimed in claim 53 , further comprising a processor.

55. A hardware assembly as claimed in claim 53 , further comprising a cache.

56. A hardware assembly as claimed in claim 53 , further comprising an SDRAM controller.

57. A hardware assembly as claimed in claim 53 , further comprising SDRAM.

58. A hardware assembly as claimed in claim 1 , further comprising a bus for communication the hardware with other hardware components.

59. A method of retrofitting hardware as claimed in claim 1 into an existing hardware assembly, the method comprising:

communicating the hardware with the hardware assembly via a bus.

60. A method of constructing a hardware assembly, the method comprising:

communicating the hardware as claimed in claim 1 with at least one other hardware component via a bus.