Memristor apparatus
A memristor apparatus comprising a plurality of meta-stable switching elements.
1. A memristor, comprising:
a plurality of meta-stable switching elements; and
an AHAH (Anti-Hebbian and Hebbian) feedback mechanism that operates on said plurality of meta-stable switching elements to comprise said memristor.
2. The memristor of claim 1 , wherein said plurality of meta-stable switching elements are driven by an AHAH rule.
3. The memristor of claim 2 , wherein said AHAH rule is provided by said AHAH feedback mechanism.
4. The memristor of claim 3 , wherein said memristor comprising said plurality of meta-stable switching elements and said AHAH feedback mechanism is employed an adaptive synaptic weight.
5. The memristor of claim 4 , wherein said memristor comprising said plurality of meta-stable switching elements and said AHAH feedback mechanism extracts independent components from a data stream.
6. The memristor of claim 4 , wherein said memristor is capable of being employed as a discrete state synapse.
7. A method of configuring a memristor, comprising:
providing a plurality of meta-stable switching elements; and
configuring an AHAH (Anti-Hebbian and Hebbian) feedback mechanism that operates on said plurality of meta-stable switching elements to comprises said memristor.
8. The method of claim 7 , further comprising:
driving said plurality of meta-stable switching elements via an AHAH rule.
9. The memristor of claim 8 wherein said AHAH rule is provided by said AHAH feedback mechanism.
10. The method of claim 9 wherein said memristor comprises said plurality of meta-stable switching elements and said AHAH feedback mechanism are employed an adaptive synaptic weight.
11. The method of claim 10 wherein said memristor comprises said plurality of meta-stable switching elements and said AHAH feedback mechanism extracts independent components from a data stream.
12. The method of claim 11 wherein said memristor is capable of being employed as a discrete state synapse.