IP Library Granted Patent US 9,105,209
Granted Patent B2
US 9,105,209 · App. 13/708,333 · Granted Aug 11, 2015

Display device

Inventors: Kazuo Kita (Osaka, JP); Genshiro Kawachi (Osaka, JP)
Assignee: Panasonic Liquid Crystal Display Co., Ltd.
G09G5/001G09G3/3688G09G3/3275G09G2300/0408G09G2300/0426G09G2310/0297G09G2320/0209G09G2320/0219
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Quick Facts
Patent No.
US 9,105,209
App. No.
13/708,333
Granted
Aug 11, 2015
Kind
B2
Abstract

In a liquid crystal display device, a data signal generation unit generates a data signal for controlling the orientation of liquid crystal. A plurality of transistors supply the data signal output from a source IC unit to a plurality of data signal lines of a liquid crystal display panel in a time sharing manner. A gate signal line controls each of the plurality of transistors. A fluctuation suppression unit is connected to the gate signal line that controls any one of the plurality of transistors, and suppresses, in accordance with a gate signal of the connected gate signal line, a voltage fluctuation in the data signal which occurs when another transistor changes from the ON state to the OFF state.

Claims (16)

1. A display device, comprising:

a data signal generation unit for generating a data signal for controlling a plurality of pixels;

a plurality of transistors for supplying the data signal output from the data signal generation unit to a plurality of data signal lines of a display panel in a time sharing manner;

a gate signal line for controlling each of the plurality of transistors; and

a fluctuation suppression unit for suppressing a voltage fluctuation in the data signal which occurs when the plurality of transistors changes from an ON state to an OFF state,

wherein the plurality of transistors include a first transistor and a second transistor, the fluctuation suppression unit connects to one of a source and a drain of the first transistor, and the gate signal line for controlling the second transistor directly connects to the second transistor with the fluctuation suppression unit.

2. The display device according to claim 1 , wherein:

the gate signal line is connected to the fluctuation suppression unit, and the second transistor, which is controlled by the gate signal line, changes from the OFF state to the ON state when the first transistor changes from the ON state to the OFF state;

the fluctuation suppression unit suppresses the voltage fluctuation in the data signal emitted from the first transistor; and

a gate signal of the gate signal line which controls the fluctuation suppression unit so as to change from the OFF state to the ON state, controls the second transistor so as to change from the OFF state to the ON state.

3. The display device according to claim 1 , wherein:

the plurality of pixels include a first pixel and a second pixel, the first pixel is controlled by a first data signal emitted from the first transistor and the second pixel is controlled by a second data signal emitted from the second transistor, the timing when the first data signal inputs the first pixel is substantially the same as the timing when the second data signal inputs the second pixel.

4. The display device according to claim 1 , wherein:

at least one of the first transistor and the second transistor is formed by a semiconductor.

5. The display device according to claim 1 , wherein:

the data signal generation unit inputs the data signal to the plurality of transistors through an output signal line.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 064292/0775 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2014
From: KITA, KAZUO; KAWACHI, GENSHIRO
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 031990/0628 →
Priority Claims (1)
JP 2011-271137 · Dec 12, 2011 · national
Continuity (1)
Related Publication 20130147780A1 · Jun 13, 2013