Granted Patent B2

US 9,110,821 · App. 14/243,107 · Granted Aug 18, 2015

Inventors: Weijun Tan (Longmont, CO); Fan Zhang (Milpitas, CA); Shaohua Yang (San Jose, CA)

Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.

G06F11/10G11B20/10009G11B20/10287G11B20/1816G11B20/1883G11B20/10296

Abstract

Claims (103)

1. A method for data processing, the method comprising:

receiving a decoded output including a first multi-bit symbol;

receiving a detected output including a second multi-bit bit symbol;

using a pre-processing circuit, calculating a first value based upon a first combination of a soft data set corresponding to the first multi-bit symbol and a second value based upon a second combination of the soft data set corresponding to the first multi-bit symbol;

using the pre-processing circuit, calculating a third value based upon a first combination of a soft data set corresponding to the second multi-bit symbol and a fourth value based upon a second combination of the soft data set corresponding to the second multi-bit symbol;

multiplying the first value by the third value to yield a first product;

multiplying the second value by the fourth value to yield a second product; and

asserting the suspect symbol indicator indicating a probability that the symbol is incorrect when at least one of the first product and the second product is negative.

2. The method of claim 1 , wherein:

the first multi-bit symbol is selected from a group consisting of: a two bit symbol, and a three bit symbol; and

the second multi-bit symbol is selected from a group consisting of: a two bit symbol, and a three bit symbol.

3. The method of claim 1 , wherein the first multi-bit symbol is a two bit symbol; wherein the soft data set corresponding to the first multi-bit symbol includes a first element, a second element, a third element, and a fourth element; and wherein:

calculating the first value includes:

selecting one of the first element and the third element that has the highest value as a first selected value;

selecting one of the second element and the fourth element that has the highest value as a second selected value; and

subtracting the second selected value from the first selected value to yield the first value;

calculating the second value includes:

selecting one of the first element and the second element that has the highest value as a third selected value;

selecting one of the third element and the fourth element that has the highest value as a fourth selected value; and

subtracting the fourth selected value from the third selected value to yield the second value.

4. The method of claim 1 , wherein the second multi-bit symbol is a two bit symbol; wherein the soft data set corresponding to the second multi-bit symbol includes a first element, a second element, a third element, and a fourth element; and wherein:

calculating the third value includes:

selecting one of the first element and the third element that has the highest value as a first selected value;

selecting one of the second element and the fourth element that has the highest value as a second selected value; and

subtracting the second selected value from the first selected value to yield the third value;

calculating the fourth value includes:

selecting one of the first element and the second element that has the highest value as a third selected value;

selecting one of the third element and the fourth element that has the highest value as a fourth selected value; and

subtracting the fourth selected value from the third selected value to yield the fourth value.

5. The method of claim 1 , wherein the method further comprises:

applying a data detection algorithm by a data detector circuit to a data set guided by the decoded output to yield the detected output; and

applying a data decoding algorithm by a data decoding circuit to a decoder input derived from the detected output to yield the symbol based decoded output.

6. The method of claim 5 , wherein the data decoding algorithm is a low density parity check algorithm; and wherein the data detection algorithm is selected from a group consisting of: a maximum a posteriori data detection algorithm, and a Viterbi data detection algorithm.

7. The method of claim 1 , wherein the suspect symbol indicator indicates a probability that the first multi-bit symbol is incorrect when at least one of the first product and the second product is negative.

8. A data processing system, the data processing system comprising:

a data detector circuit operable to apply a data detection algorithm to a symbol based data set guided by a decoded output to yield a detected output, wherein the decoded output includes at least a first multi-bit symbol, and wherein the detected output includes at least a second multi-bit symbol;

a defect detector circuit including:

a pre-processing circuit operable to:

calculate a first value based upon a first combination of a soft data set corresponding to the first multi-bit symbol a second value based upon a second combination of the soft data set corresponding to the first multi-bit symbol;

calculate a third value based upon a first combination of a soft data set corresponding to the second multi-bit symbol and a fourth value based upon a second combination of the soft data set corresponding to the second multi-bit symbol;

multiply the first value by the third value to yield a first product;

multiply the second value by the fourth value to yield a second product; and

assert a suspect symbol indicator indicating a probability that the symbol is incorrect when at least one of the first product and the second product is negative;

a binary data detection circuit operable to provide a defect indicator corresponding to a probable defect identified based on the suspect symbol indicator; and

a data decoder circuit operable to apply a data decode algorithm to a decoder input derived from the detected output modified based on the defect indicator to yield the decoded output.

9. The data processing system of claim 8 , wherein the soft data set corresponding to the first multi-bit symbol includes a first element, a second element, a third element, and a fourth element; and wherein:

calculating the first value includes:

selecting one of the first element and the third element that has the highest value as a first selected value;

selecting one of the second element and the fourth element that has the highest value as a second selected value; and

subtracting the second selected value from the first selected value to yield the first value;

calculating the second value includes:

selecting one of the first element and the second element that has the highest value as a third selected value;

selecting one of the third element and the fourth element that has the highest value as a fourth selected value; and

subtracting the fourth selected value from the third selected value to yield the second value.

10. The data processing system of claim 8 , wherein the soft data set corresponding to the second two bit symbol includes a first element, a second element, a third element, and a fourth element; and wherein:

calculating the third value includes:

selecting one of the first element and the third element that has the highest value as a first selected value;

selecting one of the second element and the fourth element that has the highest value as a second selected value; and

subtracting the second selected value from the first selected value to yield the third value;

calculating the fourth value includes:

selecting one of the first element and the second element that has the highest value as a third selected value;

selecting one of the third element and the fourth element that has the highest value as a fourth selected value; and

subtracting the fourth selected value from the third selected value to yield the fourth value.

11. The data processing system of claim 8 , wherein the multi-bit symbols are selected from a group consisting of: two bit symbols, and three bit symbols.

12. The data processing system of claim 8 , wherein the suspect symbol indicator indicates a probability that a symbol is incorrect when a combination of the decoded output and the detected output is negative.

13. The data processing system of claim 8 , wherein the system is implemented as an integrated circuit.

14. The data processing system of claim 8 , wherein the system is implemented as part of a storage device.

15. The data processing system of claim 8 , wherein the data decoder circuit is a low density parity check decoder circuit.

16. The data processing system of claim 8 , wherein the data detector circuit is selected from a group consisting of: a Viterbi algorithm data detector circuit, and a maximum a posteriori data detector circuit.

17. A storage device, the storage device comprising:

a storage medium;

a read/write head assembly operable to sense information from the storage medium and to provide a corresponding continuous signal;

an analog to digital converter circuit operable to sample the continuous signal synchronous to a sampling clock to yield a set of digital samples;

an equalizer circuit operable to equalize the set of digital samples and to provide a corresponding symbol based output;

a data detector circuit operable to apply a data detection algorithm to the symbol based output guided by a decoded output to yield a detected output, wherein the decoded output includes at least a first multi-bit symbol, and wherein the detected output includes at least a second multi-bit symbol;

a defect detector circuit including:

a pre-processing circuit operable to:

calculate a first value based upon a first combination of a soft data set corresponding to the first multi-bit symbol a second value based upon a second combination of the soft data set corresponding to the first multi-bit symbol;

calculate a third value based upon a first combination of a soft data set corresponding to the second multi-bit symbol and a fourth value based upon a second combination of the soft data set corresponding to the second multi-bit symbol;

multiply the first value by the third value to yield a first product;

multiply the second value by the fourth value to yield a second product; and

assert a suspect symbol indicator indicating a probability that the symbol is incorrect when at least one of the first product and the second product is negative;

a binary data detection circuit operable to provide a defect indicator corresponding to a probable defect identified based on the suspect symbol indicator; and

a data decoder circuit operable to apply a data decode algorithm to a decoder input derived from the detected output modified based on the defect indicator to yield the decoded output.

18. The storage device of claim 17 , wherein the soft data set corresponding to the first multi-bit symbol includes a first element, a second element, a third element, and a fourth element; and wherein:

calculating the first value includes:

selecting one of the first element and the third element that has the highest value as a first selected value;

selecting one of the second element and the fourth element that has the highest value as a second selected value; and

subtracting the second selected value from the first selected value to yield the first value;

calculating the second value includes:

selecting one of the first element and the second element that has the highest value as a third selected value;

selecting one of the third element and the fourth element that has the highest value as a fourth selected value; and

subtracting the fourth selected value from the third selected value to yield the second value.

19. The storage device of claim 17 , wherein the soft data set corresponding to the second two bit symbol includes a first element, a second element, a third element, and a fourth element; and wherein:

calculating the third value includes:

selecting one of the first element and the third element that has the highest value as a first selected value;

selecting one of the second element and the fourth element that has the highest value as a second selected value; and

subtracting the second selected value from the first selected value to yield the third value;

calculating the fourth value includes:

selecting one of the first element and the second element that has the highest value as a third selected value;

selecting one of the third element and the fourth element that has the highest value as a fourth selected value; and

subtracting the fourth selected value from the third selected value to yield the fourth value.

20. The storage device of claim 17 , wherein the multi-bit symbols are selected from a group consisting of: two bit symbols, and three bit symbols.

Assignments (10)

Continuity (3)