Nonvolatile semiconductor memory device and manufacturing method thereof
View Patent ↗According to one embodiment, a plurality of memory cell transistors including a floating gate and a control gate and a plurality of peripheral circuit transistors including a lower electrode portion and an upper electrode portion are included. The floating gate includes a first polysilicon region, and the lower electrode includes a second polysilicon region. The first polysilicon region is a p-type semiconductor in which boron is doped, and the second polysilicon region is an n-type semiconductor in which phosphorus and boron are doped.
1. A nonvolatile semiconductor memory device comprising:
memory cell transistors including a floating gate and a control gate; and
a peripheral circuit transistor including a lower electrode and an upper electrode, wherein
the floating gate includes a first polysilicon region that includes a p-type semiconductor that is doped with boron,
the lower electrode includes a second polysilicon region that includes an n-type semiconductor, the second polysilicon region of the lower electrode being doped with phosphorus and boron,
a concentration of boron at a surface point of the second polysilicon region is higher than a concentration of boron at an inner point of the second polysilicon region, and
a concentration of phosphorus at the surface point of the second polysilicon region is higher than a concentration of phosphorus at the inner point of the second polysilicon region.
2. The device according to claim 1 ,
wherein a concentration of an n-type impurity in the second polysilicon region is between about 1×10 20 atms/cm 3 and about 1×10 22 atms/cm 3 .
3. The device according to claim 1 , wherein the second polysilicon region includes a concentration of phosphorus of between about 1×10 20 atms/cm 3 and about 1×10 22 atms/cm 3 and a concentration of boron of equal to or less than 1×10 19 atms/cm 3 .
4. A nonvolatile semiconductor memory device comprising:
memory cell transistors including a floating gate and a control gate; and
a peripheral circuit transistor including a lower electrode and an upper electrode, wherein
the floating gate includes a first polysilicon region that includes a p-type semiconductor that is doped with boron,
the lower electrode includes a second polysilicon region that includes an n-type semiconductor, the second polysilicon region of the lower electrode being doped with phosphorus and boron,
the second polysilicon region includes a concentration of boron and a concentration of phosphorus that both decrease in a direction extending from a surface of the second polysilicon region to a center region of the second polysilicon region.
5. The device according to claim 1 , wherein the first polysilicon region includes one or more of the elements selected from a group consisting of carbon, nitrogen and oxygen.
6. The device according to claim 5 ,
wherein a concentration of carbon or nitrogen contained in the first polysilicon region is between about 5×10 19 atms/cm 3 and about 5×10 21 atms/cm 3 , and
the carbon or nitrogen is disposed in a region between about zero and about 5 nm to 35 nm from a surface of the first polysilicon region.
7. The device according to claim 1 , wherein the first polysilicon region further comprises a first doped region that has a concentration of carbon or nitrogen between about 5×10 19 atms/cm 3 and about 5×10 21 atms/cm 3 , and the first doped region is disposed between a bottom surface of the first polysilicon region and a depth of 5 nm to 35 nm from the bottom surface of the first polysilicon region.
8. The device according to claim 1 ,
wherein the first polysilicon region includes a dividing layer containing oxygen, and
the dividing layer in each memory cell transistor is provided at a same distance from a main surface of a semiconductor substrate on which the memory cell transistors are provided.
9. A nonvolatile semiconductor memory device comprising:
memory cell transistors including a floating gate and a control gate; and
a peripheral circuit transistor including a lower electrode and an upper electrode, wherein
the floating gate includes a first polysilicon region that includes a p-type semiconductor that is doped with boron,
the lower electrode includes a second polysilicon region that includes an n-type semiconductor, the second polysilicon region of the lower electrode being doped with phosphorus and boron, and
a ratio of a concentration of phosphorous to a concentration of boron in the second polysilicon region is greater than 10.
10. The device according to claim 1 , wherein the first and second polysilicon regions further comprise a crystalline silicon material.
11. The device according to claim 1 , wherein the surface point of the second polysilicon region is located on a surface that faces a main surface of a semiconductor substrate on which the memory cell transistors are provided.