IP Library Granted Patent US 9,166,706
Granted Patent B2
US 9,166,706 · App. 14/198,059 · Granted Oct 20, 2015

System and method for testing a radio frequency integrated circuit

Inventor: Hans Peter Forstner (Steinhoering, DE)
Assignee: Infineon Technologies AG
H04B17/00G01R31/2822G01R31/3187
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Quick Facts
Patent No.
US 9,166,706
App. No.
14/198,059
Granted
Oct 20, 2015
Kind
B2
Abstract

In an embodiment, a method of testing a radio frequency integrated circuit (RFIC) includes generating high frequency test signals using the on-chip test circuit, measuring signal levels using on-chip power detectors, and controlling and monitoring the on-chip test circuit using low frequency signals. The RFIC circuit is configured to operate at high frequencies, and an on-chip test circuit that includes frequency generation circuitry configured to operate during test modes.

Claims (45)

1. A method of testing a radio frequency integrated circuit (RFIC) circuit comprising an RF circuit configured to operate at high frequencies, and an on-chip test circuit comprising frequency generation circuitry configured to operate during test modes, the method comprising:

generating high frequency test signals using the on-chip test circuit;

measuring signal levels using on-chip power detectors; and

controlling and monitoring the on-chip test circuit using low frequency signals.

2. The method of claim 1 , wherein the high frequencies comprise high frequencies greater than 10 GHz, and the low frequency signals comprise frequencies less than 1 MHz.

3. The method of claim 1 , wherein:

controlling and monitoring the on-chip test circuit using the low frequency signals comprises applying a low-frequency test signal to an input of a mixer of the on-chip test circuit; and

generating high frequency test signals using the on-chip test circuit comprises coupling a local oscillator of the on-chip test circuit to a further input of the mixer of the on-chip test circuit.

4. The method of claim 3 , wherein generating high frequency test signals using the on-chip test circuit further comprises coupling an output of the mixer of the on-chip test circuit to an RF input of the RF circuit.

5. The method of claim 3 , wherein generating high frequency test signals using the on-chip test circuit further comprises coupling an output of the mixer of the on-chip test circuit to a local oscillator input of the RF circuit.

6. The method of claim 3 , further comprising setting a signal power of the local oscillator of the on-chip test circuit comprising

measuring an output level of a test variable gain amplifier coupled between the local oscillator and the further input of the mixer via a first power detector comprising an output coupled to a low frequency external interface of the on-chip test circuit; and

adjusting a gain of test variable gain amplifier based on the measurement to provide a target local oscillator signal level.

7. A method of testing a radio frequency integrated circuit (RFIC) circuit comprising an RF circuit configured to operate at high frequencies, and an on-chip test circuit comprising frequency generation circuitry configured to operate only during test modes, the method comprising:

generating all high frequency test signals using the on-chip test circuit;

measuring signal levels using on-chip power detectors; and

controlling and monitoring the on-chip test circuit using low frequency signals.

8. The method of claim 7 , wherein the high frequencies comprise high frequencies greater than 10 GHz, and the low frequency signals comprise frequencies less than 1 MHz.

9. The method of claim 7 , further comprising testing a high frequency signal path of the RF circuit using only low-frequency test equipment.

10. The method of claim 9 , wherein analog interfaces of the low-frequency test equipment communicate with the RFIC using only frequencies less than 1 MHz.

11. The method of claim 7 , wherein:

controlling and monitoring the on-chip test circuit using the low frequency signals comprises applying a low-frequency test signal to an input of a mixer of the on-chip test circuit; and

generating high frequency test signals using the on-chip test circuit comprises coupling a local oscillator of the on-chip test circuit to a further input of the mixer of the on-chip test circuit.

12. The method of claim 11 , wherein generating high frequency test signals using the on-chip test circuit further comprises coupling an output of the mixer of the on-chip test circuit to an RF input of the RF circuit.

13. The method of claim 11 , wherein generating high frequency test signals using the on-chip test circuit further comprises coupling an output of the mixer of the on-chip test circuit to a local oscillator input of the RF circuit.

14. A method of testing a radio frequency integrated circuit (RFIC) comprising a RF receiver and a built-in test circuit, the method comprising operating the RFIC in a test mode, operating the RFIC in the test mode comprising:

coupling an LO input of the RF receiver to an output of a test oscillator of the built-in test circuit;

coupling an RF input of the RF receiver to an output of a mixer of the built-in test circuit, wherein the mixer of the built-in test circuit comprises a first input coupled to the output of the test oscillator; and

applying a test frequency from a low-frequency external interface of the built-in test circuit to a second input of the mixer of the built-in test circuit.

15. The method of claim 14 , further comprising changing a mode of operation of the RFIC from the test mode to a normal mode, changing the mode of operation comprising:

shutting down the test oscillator; and

decoupling the output of the test oscillator of the built-in test circuit from the LO input of the RF receiver.

16. The method of claim 14 , further comprising setting an LO signal power, setting the LO power comprising;

measuring an output level of a test VGA coupled between the test oscillator and the LO input via a first power detector comprising an output coupled to the low frequency external interface of the built-in test circuit; and

adjusting a gain of test VGA based on the measurement to provide a target LO signal level.

17. The method of claim 14 , further comprising determining a conversion gain, determining a conversion gain comprising:

measuring a first signal level at the output of the mixer, via second power detector comprising an output coupled to a low-frequency interface of the built-in test circuit;

measuring a second signal level at an output of the receiver; and

determining conversion gain based on measuring the first signal level and measuring the second signal level.

18. The method of claim 14 , further comprising setting a frequency of the test oscillator, setting the frequency comprising:

dividing an output frequency of the oscillator;

providing the divided oscillator frequency to the low-frequency external interface; and

measuring the divided oscillator frequency; and

adjusting a frequency setting to the test oscillator based on the measuring.

19. The method of claim 18 , wherein adjusting the frequency comprises writing a value to a digital-to-analog (DAC) converter comprising an output coupled to a frequency control input of the test oscillator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2014
From: FORSTNER, HANS-PETER
To: INFINEON TECHNOLOGIES AG
Reel/Frame 032389/0946 →
Continuity (2)
Division 12952261 · Nov 23, 2010
Related Publication 20140187170A1 · Jul 3, 2014