IP Library Granted Patent US 9,184,012
Granted Patent B2
US 9,184,012 · App. 13/720,098 · Granted Nov 10, 2015

Integrated circuit fuse and method of fabricating the integrated circuit fuse

Inventor: Yigong Wang (Rutland, MA)
Assignee: Allegro Microsystems, LLC
H01H69/022H01H85/0047H01H2085/0414H01H2085/466Y10T29/49107
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Quick Facts
Patent No.
US 9,184,012
App. No.
13/720,098
Granted
Nov 10, 2015
Kind
B2
Abstract

A fuse formed as part of an integrated circuit has cavities disposed to the sides of the fuse to provide more reliable operation with less chance of re-connection. A method of providing the fuse is also described.

Claims (31)

1. A fuse disposed over a substrate of an integrated circuit, comprising:

a conductive trace in a fuse-level metal layer of the integrated circuit, wherein the conductive trace comprises a fusible portion having a higher resistance than other portions of the conductive trace, and wherein the fusible portion comprises a longest dimension;

a dielectric structure disposed over the fusible portion and beyond the fusible portion in a direction parallel to a major surface of the substrate; and

a first cavity into the dielectric structure, the first cavity configured to capture debris from the fusible portion when the fusible portion is fused, wherein the first cavity is proximate to the fusible portion and separated from the fusible portion by a first separation wall, wherein the first cavity has a depth to at least a depth of the fuse-level metal layer with a deeper direction being in a direction toward the substrate, wherein the entire first cavity is disposed to a first side of the fusible portion in a direction parallel to a major surface of the substrate and perpendicular to the longest dimension of the fusible portion such that no part of the first cavity is over the fusible portion, wherein the first separation wall has a thickness selected to result in fracture, the fracture causing a fracture opening in the first separation wall and capture of debris from the fusible portion within the first cavity when the fusible portion is fused.

2. The fuse of claim 1 , wherein the selected thickness of the first separation wall is within about +/− ten percent of 1.2 micrometers.

3. The fuse of claim 2 , wherein the fusible portion has a width within about +/− ten percent of 1.0 micrometers.

4. The fuse of claim 1 , wherein the first cavity extends to a depth at or below the fuse-level metal layer.

5. The fuse of claim 1 , wherein the first cavity extends to the depth of the fuse-level metal layer, wherein the first cavity has a deepest end nearest to the substrate, and wherein the deepest end is bounded by a metal bounding portion of the fuse-level metal layer.

6. The fuse of claim 1 , wherein the first cavity extends to a depth below the fuse-level metal layer, and wherein the first cavity has a deepest end nearest to the substrate, and wherein the deepest end is bounded by a metal bounding portion of another metal layer deeper than the fuse-level metal layer.

7. The fuse of claim 1 , wherein the first cavity extends to a depth below the fuse-level metal layer, and wherein the first cavity has a deepest end nearest to the substrate, and wherein the deepest end is bounded by the substrate.

8. The fuse of claim 1 , further comprising a second cavity into the dielectric structure, the second cavity configured to capture debris from the fusible portion when the fusible portion is fused, wherein the second cavity is proximate to the fusible portion and separated from the fusible portion by a second separation wall, wherein the second cavity has a depth to at least a depth of the fuse-level metal layer, wherein the entire second cavity is disposed to a second side of the fusible portion different than the first side in a direction parallel to the major surface of the substrate and perpendicular to the longest dimension of the fusible portion such that no part of the second cavity is over the fusible portion, wherein the first separation wall and the second separation wall have a thickness selected to result in fracture, the fracture causing a fracture opening in at least one of the first separation wall and the second separation wall and capture of debris from the fusible portion within at least one of the first cavity or the second cavity when the fusible portion is fused.

9. The fuse of claim 8 , wherein the selected thickness of the first and second separation walls is within about +/− ten percent of 1.2 micrometers.

10. The fuse of claim 8 , wherein the first and second cavities extend to the depth of the fuse-level metal layer, wherein the first and second cavities have respective deepest ends nearest to the substrate, and wherein the deepest ends are bounded by respective bounding metal portions of the fuse-level metal layer.

11. The fuse of claim 8 , wherein the first and second cavities extend to the depth below the fuse-level metal layer, wherein the first and second cavities have respective deepest ends nearest to the substrate, and wherein the deepest ends are bounded by respective a bounding metal portions of another metal layer deeper than the fuse-level metal layer.

12. The fuse of claim 8 , wherein the first and second cavities extend to the depth below the fuse-level metal layer, wherein the first and second cavities have respective deepest ends nearest to the substrate, and wherein the deepest ends are bounded by the substrate.

13. A method of fabricating a fuse over a substrate of an integrated circuit, comprising:

forming a conductive trace in a fuse-level metal layer of the integrated circuit, wherein the fuse-level metal layer is disposed over a substrate of the integrated circuit, wherein the conductive trace comprises a fusible portion having a higher resistance than other portions of the conductive trace, and wherein the fusible portion comprises a longest dimension;

forming a dielectric structure over the fusible portion and beyond the fusible portion in a direction parallel to a major surface of the substrate; and

forming a first cavity into the dielectric structure, the first cavity configured to capture debris from the fusible portion when the fusible portion is fused, wherein the first cavity is proximate to the fusible portion and separated from the fusible portion by a first separation wall, wherein the first cavity has a depth to at least a depth of the fuse-level metal layer with a deeper direction being in a direction toward the substrate, wherein the entire first cavity is disposed to a first side of the fusible portion in a direction parallel to a major surface of the substrate and perpendicular to the longest dimension of the fusible portion such that no part of the first cavity is over the fusible portion, wherein the first separation wall has a thickness selected to result in fracture, the fracture causing a fracture opening in the first separation wall and capture of debris from the fusible portion within the first cavity when the fusible portion is fused.

14. The method of claim 13 , wherein the selected thickness of the first separation wall is within about +/− ten percent of 1.2 micrometers.

15. The method of claim 14 , wherein the fusible portion has a width within about +/− ten percent of 1.0 micrometers.

16. The method of claim 13 , wherein the first cavity extends to a depth at or below the fuse-level metal layer.

17. The method of claim 13 , wherein the first cavity extends to the depth of the fuse-level metal layer, wherein the first cavity has a deepest end nearest to the substrate, and wherein the deepest end is bounded by a bounding metal portion of the fuse-level metal layer.

18. The method of claim 13 , wherein the first cavity extends to a depth below the fuse-level metal layer, and wherein the first cavity has a deepest end nearest to the substrate, and wherein the deepest end is bounded by a bounding metal portion of another metal layer deeper than the fuse-level metal layer.

19. The method of claim 13 , wherein the first cavity extends to a depth below the fuse-level metal layer, and wherein the first cavity has a deepest end nearest to the substrate, and wherein the deepest end is bounded by the substrate.

20. The method of claim 13 , further comprising:

forming a second cavity into the dielectric structure, the second cavity configured to capture debris from the fusible portion when the fusible portion is fused, wherein the second cavity is proximate to the fusible portion and separated from the fusible portion by a second separation wall, wherein the second cavity has a depth to at least a depth of the fusible portion, wherein the entire second cavity is disposed to a second side of the fusible portion different than the first side in a direction parallel to the major surface of the substrate and perpendicular to the longest dimension of the fusible portion such that no part of the second cavity is over the fusible portion, wherein the first separation wall and the second separation wall have a thickness selected to result in fracture, the fracture causing a fracture opening in at least one of the first separation wall and the second separation wall and capture of debris from the fusible portion within at least one of the first cavity or the second cavity when the fusible portion is fused.

21. The method of claim 13 , wherein the selected thickness of the first and second separation walls is within about +/− ten percent of 1.2 micrometers.

22. The method of claim 13 , wherein the first and second cavities extend to the depth of the fuse-level metal layer, wherein the first and second cavities have respective deepest ends nearest to the substrate, and wherein the deepest ends are bounded by respective bounding metal portions of the fuse-level metal layer.

23. The method of claim 15 , wherein the first and second cavities extend to the depth below the fuse-level metal layer, wherein the first and second cavities have respective deepest ends nearest to the substrate, and wherein the deepest ends are bounded by respective a bounding portions of another metal layer deeper than the fuse-level metal layer.

24. The method of claim 15 , wherein the first and second cavities extend to the depth below the fuse-level metal layer, wherein the first and second cavities have respective deepest ends nearest to the substrate, and wherein the deepest ends are bounded by the substrate.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS AT REEL 053957/FRAME 0874 Recorded Nov 1, 2023
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 065420/0572 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2023
From: ALLEGRO MICROSYSTEMS, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 064068/0459 →
RELEASE OF SECURITY INTEREST IN PATENTS (R/F 053957/0620) Recorded Jun 22, 2023
From: MIZUHO BANK, LTD., AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 064068/0360 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 053957/0874 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: MIZUHO BANK LTD., AS COLLATERAL AGENT
Reel/Frame 053957/0620 →
CONVERSION AND NAME CHANGE Recorded Apr 10, 2013
From: ALLEGRO MICROSYSTEMS, INC.
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 030426/0178 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2012
From: WANG, YIGONG
To: ALLEGRO MICROSYSTEMS, INC.
Reel/Frame 029509/0478 →
Continuity (1)
Related Publication 20140167906A1 · Jun 19, 2014