Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.
1. A Multicore Shared Memory Controller (MSMC) comprising:
a plurality of CPU interfaces for connection to respective central processing units for receiving CPU transaction requests;
at least one slave interface for connection to a corresponding slave device serving as a shared resource;
a multicore shared memory controller datapath connected to said plurality of CPU interfaces and said at least one slave interface, said multicore shared memory controller datapath operable to
receive CPU transaction requests from central processing units via a corresponding CPU interface,
arbitrate between master components and shared resources and operable to enforce data consistency when data blocks are modified for a resource slave,
reserve two back to back slots for each command processing a single cache line fill request from one of said plurality of CPU interfaces, and
insert a dummy command cycle if a memory access from one of the plurality of CPU interfaces requests less than a cache line size.
2. The Multicore Shared Memory Controller of claim 1 , wherein:
said multicore shared memory controller datapath is further operable to segment non cacheline aligned received CPU transaction requests.
3. The Multicore Shared Memory Controller of claim 1 , wherein:
said multicore shared memory controller datapath is further operable to perform parallel transactions to multiple slaves in an atomic fashion.
4. The Multicore Shared Memory Controller of claim 1 , further comprising:
a shared on chip memory; and
said multicore shared memory controller datapath is further operable to employ said shared on chip memory as scratch memory for all master components, with the memory addressing space segmented into a plurality of parallel banks where the data width is sized to be half of the cache line size, and the segmentation boundaries for the on chip memory is aligned with the bank data width size.
5. The Multicore Shared Memory Controller of claim 1 , further comprising:
an off chip memory interface; and
said multicore shared memory controller datapath is further operable to process all master's accesses to off chip memory via said off chip memory interface with an optimum access size equal to or larger than the cache line size, and to segment the access commands to the off chip memory on cache line boundaries.
6. The Multicore Shared Memory Controller of claim 5 , wherein:
said multicore shared memory controller datapath is further operable to reserve two back to back slots for two commands processing two cache line fills.