IP Library Granted Patent US 9,237,039
Granted Patent B2
US 9,237,039 · App. 14/307,098 · Granted Jan 12, 2016

Transceiver suitable for IO-Link devices and related IO-Link device

Inventors: Salvatore Cassata (Palermo, IT); Francesco Pulvirenti (Acireale, IT); Salvatore Giuseppe Privitera (Catania, IT)
Assignee: STMICROELECTRONICS S.R.L.
H04L25/0292H02H9/04H04B3/00H04L25/028Y10T29/49169
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Quick Facts
Patent No.
US 9,237,039
App. No.
14/307,098
Granted
Jan 12, 2016
Kind
B2
Abstract

A transceiver is connectable to a cable with at least three wires. The transceiver may include a controlled output stage including a high-side leg, having two P-type transistors coupled in series and having a common current terminal, coupled between an output pin and a positive supply pin. The P-type transistors have body regions coupled to the common current terminal of the high-side leg. A low-side leg, includes two N-type transistors coupled in series and having a common current terminal, coupled between the output pin and a negative supply pin. The N-type transistors have body regions coupled to the common current terminal of the low-side leg. The protection circuit also includes a voltage clamper coupled between the common current terminals.

Claims (44)

1. A transceiver suitable for IO-Link™ devices, connectable to a cable with at least three wires, comprising:

a positive supply pin connectable to a positive supply wire of the cable on which a positive supply voltage is made available;

a negative supply pin connectable to a negative supply wire of the cable on which a negative supply voltage is made available;

at least one input/output pin connectable to a digital data wire of the cable configured to receive/transmit data signals switching between the positive supply voltage and negative supply voltage from/to IO-Link™ devices connected to the cable;

inner functional blocks;

an internal positive voltage line;

an internal negative voltage line; and

a controlled output stage configured to connect said at least one input/output pin to said positive supply pin or to said negative supply pin, including a protection circuit for said inner functional blocks against reverse polarity due to a wrong connection of said positive and negative supply pins to respective wires of the cable;

said controlled output stage comprising

a high-side leg, comprising two P-type transistors connected in series between them such as to have a common current terminal, coupled between said at least one input/output pin and said positive supply pin, the common current terminal being connected to said internal positive voltage line, said P-type transistors having body regions being shorted to the common current terminal, and

a low-side leg, comprising two N-type transistors connected in series between them such as to have a common current terminal, coupled between said at least one input/output pin and said negative supply pin, the common current terminal being connected to said internal negative voltage line, said N-type transistors having body regions being shorted to the common current terminal; and

a driver comprising a first current path extending between a positive supply terminal and the common current terminal of the high-side leg, and a second current path extending between a negative supply terminal and common current terminal of the low-side leg, and being configured to turn on/off said two P-type and two N-type transistors to allow transmission on the digital data wire;

said protection circuit comprising a voltage clamper connected between the common current terminal for said high-side leg and the common current terminal for said low-side leg, configured to enter in a conduction state in case of overvoltage on the internal negative and positive supply voltage lines.

2. The transceiver of claim 1 , wherein said voltage clamper comprises a power transistor connected to short said common current terminals when in a conduction state; and a bias Zener diode connected between a control terminal of said power transistor and the common current terminal of said high-side leg, configured to enter in a conduction state and to cause a voltage drop suitable for turning on said power transistor in case of an overvoltage on said internal negative and positive supply voltage lines.

3. The transceiver of claim 2 , further comprising a bias resistor connected between said control terminal of the power transistor and the common current terminal of said low-side leg.

4. The transceiver of claim 1 , wherein said at least one input/output pin comprises a high-side input/output pin and a low-side input/output pin, both connectable to the data wire of the cable, said high-side leg being connected between said high-side input/output pin and said positive supply pin, and said low-side leg being connected between said low-side input/output pin and said negative supply pin.

5. The transceiver of claim 1 , wherein said protection circuit is realized in integrated form along with said inner functional blocks.

6. An electronic device connectable to a cable with at least three wires, comprising:

a positive supply pin connectable to a positive supply wire of the cable;

a negative supply pin connectable to a negative supply wire of the cable;

at least one output pin connectable to a digital data wire of the cable; and

a controlled output stage comprising

a high-side leg, comprising two P-type transistors coupled in series and having a common current terminal, coupled between said at least one output pin and said positive supply pin, said P-type transistors having body regions coupled to the common current terminal,

a low-side leg, comprising two N-type transistors coupled in series and having a common current terminal, coupled between said at least one output pin and said negative supply pin, said N-type transistors having body regions coupled to the common current terminal,

a driver comprising a first current path extending between a positive supply terminal and the common current terminal of the high-side leg, and a second current path extending between a negative supply terminal and common current terminal of the low-side leg, and being configured to turn on/off said two P-type and two N-type transistors, and

a protection circuit comprising a voltage clamper coupled between the common current terminal for said high-side leg and the common current terminal for said low-side leg.

7. The electronic device of claim 6 , further comprising inner functional blocks; and wherein said protection circuit is configured for protecting said inner functional blocks against reverse polarity due to a wrong connection of said positive and negative supply pins to respective wires of the cable.

8. The electronic device of claim 6 , wherein said voltage clamper comprises a power transistor coupled to short the common current terminals when in a conduction state; and a Zener diode coupled between a control terminal of said power transistor and the common current terminal of said high-side leg.

9. The electronic device of claim 8 , further comprising a bias resistor coupled between the control terminal of said power transistor and the common current terminal of said low-side leg.

10. The electronic device of claim 6 , wherein said at least one output pin comprises a high-side output pin and a low-side output pin, both connectable to the data wire of the cable, said high-side leg being coupled between said high-side output pin and said positive supply pin, and said low-side leg being coupled between said low-side output pin and said negative supply pin.

11. The electronic device of claim 6 , wherein said protection circuit is realized in integrated form.

12. The electronic device of claim 6 , wherein said positive supply pin, negative supply pin, at least one output pin, and controlled output stage define an IO-Link™ device transceiver.

13. The electronic device of claim 12 , further comprising a microcontroller coupled to said IO-Link™ device transceiver.

14. An method for making an electronic device connectable to a cable with at least three wires, the electronic device comprising a positive supply pin connectable to a positive supply wire of the cable, a negative supply pin connectable to a negative supply wire of the cable, and at least one output pin connectable to a digital data wire of the cable; the method comprising:

forming a controlled output stage comprising

a high-side leg, comprising two P-type transistors coupled in series and having a common current terminal, coupled between the at least one output pin and the positive supply pin, the P-type transistors having body regions coupled to the common current terminal,

a low-side leg, comprising two N-type transistors coupled in series and having a common current terminal, coupled between the at least one output pin and the negative supply pin, the N-type transistors having body regions coupled to the common current terminal,

a driver comprising a first current path extending between a positive supply terminal and the common current terminal of the high-side leg, and a second current path extending between a negative supply terminal and common current terminal of the low-side leg, and being configured to turn on/off the two P-type and two N-type transistors to allow transmission on the digital data wire, and

a protection circuit comprising a voltage clamper coupled between the common current terminal for the high-side leg and the common current terminal for the low-side leg.

15. The method of claim 14 , wherein the protection circuit is configured for protecting inner functional blocks of the electronic device against reverse polarity due to a wrong connection of the positive and negative supply pins to respective wires of the cable.

16. The method of claim 14 , wherein the voltage clamper comprises a power transistor coupled to short the common current terminals when in a conduction state; and a Zener diode coupled between a control terminal of the power transistor and the common current terminal of the high-side leg.

17. The method of claim 16 , further comprising a bias resistor coupled between the control terminal of the power transistor and the common current terminal of the low-side leg.

18. The method of claim 14 , wherein the protection circuit is realized in integrated form.

19. The method of claim 14 , wherein the positive supply pin, negative supply pin, at least one output pin, and controlled output stage define an IO-Link™ device transceiver.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2022
From: STMICROELECTRONICS S.R.L.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 061828/0243 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2014
From: CASSATA, SALVATORE; PULVIRENTI, FRANCESCO; PRIVITERA, SALVATORE GIUSEPPE
To: STMICROELECTRONICS S.R.L.
Reel/Frame 033182/0925 →
Priority Claims (1)
IT MI2013A1077 · Jun 27, 2013 · national
Continuity (1)
Related Publication 20150003503A1 · Jan 1, 2015