IP Library Granted Patent US 9,277,639
Granted Patent B2
US 9,277,639 · App. 14/433,342 · Granted Mar 1, 2016

Semiconductor circuit board, semiconductor device using the same, and method for manufacturing semiconductor circuit board

Inventors: Hiromasa Kato (Nagareyama, JP); Masanori Hoshino (Yokohama, JP)
Assignees: KABUSHIKI KAISHA TOSHIBA; TOSHIBA MATERIALS CO., LTD.
H05K1/0207C04B37/026H01L21/4857H01L23/3735H01L23/49822H01L23/49838H01L23/49866H01L24/32H01L24/83H05K1/0306H05K1/092C04B2235/407C04B2235/6581C04B2235/96C04B2235/9607C04B2237/125C04B2237/127C04B2237/343C04B2237/366C04B2237/368C04B2237/704C04B2237/86H01L21/4807H01L23/15H01L24/29H01L25/072H01L2224/29124H01L2224/29139H01L2224/29147H01L2224/32225H01L2224/83801H01L2924/01322H01L2924/1033H01L2924/10253H01L2924/10272H01L2924/1305H01L2924/13055H05K2201/0929
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Quick Facts
Patent No.
US 9,277,639
App. No.
14/433,342
Granted
Mar 1, 2016
Kind
B2
Abstract

The present invention provides a semiconductor circuit board in which a conductor portion is provided on an insulating substrate, wherein a surface roughness of a semiconductor element-mounting section of the conductor portion is 0.3 μm or lower in arithmetic average roughness Ra, 2.5 μm or lower in ten-point average roughness Rzjis, 2.0 μm or smaller in maximum height Rz, and 0.5 μm or lower in arithmetic average waviness Wa. Further, assuming that a thickness of the insulating substrate is t1 and a thickness of the conductor portion is t2, the thickness of t1 and t2 satisfy a relation: 0.1≦t2/t1≦50. Due to above structure, even if an amount of heat generation of the semiconductor element is increased, there can be provided a semiconductor circuit board and a semiconductor device having excellent TCT characteristics.

Claims (17)

1. A semiconductor circuit board in which a conductor portion is provided on an insulating substrate, wherein a surface roughness of a semiconductor element-mounting section of the conductor portion is 0.3 μm or lower in arithmetic average roughness Ra, 2.5 μm or lower in ten-point average roughness Rzjis, 2.0 μm or smaller in maximum height Rz, and 0.5 μm or lower in arithmetic average waviness Wa.

2. The semiconductor circuit board according to claim 1 , wherein assuming that a thickness of the insulating substrate is t1 and a thickness of the conductor portion is t2, the thickness of t1 and t2 satisfy a relation: 0.1≦t2/t1≦50.

3. The semiconductor circuit board according to claim 1 , wherein a cross-sectional angle of a lateral-side edge of the conductor portion is 45° or smaller.

4. The semiconductor circuit board according to claim 1 , wherein the conductor portion is made of a metal plate, whereas the insulating substrate is made of a ceramic substrate, and a region (width) of a bonding layer, for joining the metal plate and the ceramic substrate, protruding from the metal plate is 0.2 mm or smaller.

5. The semiconductor circuit board according to claim 1 , wherein the insulating substrate is composed of one of an alumina substrate, an aluminum nitride substrate, a silicon nitride substrate, and an insulating resin substrate.

6. The semiconductor circuit board according to claim 1 , wherein the conductor portion is composed of one of copper, copper alloy, aluminum, and aluminum alloy.

7. A semiconductor device in which a semiconductor element is mounted on a conductor portion of a semiconductor circuit board according to claim 1 .

8. The semiconductor device according to claim 7 , wherein the semiconductor element is composed of one or more than one element selected from a group consisting of an Si element, a GaN element, and an SiC element.

9. The semiconductor device according to claim 7 , wherein the semiconductor element is bonded to the conductor portion with a bonding material interposed therebetween.

10. The semiconductor device according to claim 7 , wherein the semiconductor element is directly bonded to the conductor portion without a bonding material interposed therebetween.

11. A method for manufacturing a semiconductor circuit board, comprising:

a conductor portion formation step of forming a conductor portion on an insulating substrate;

a surface treatment step of setting a surface roughness of a semiconductor element-mounting section of the conductor portion to 0.3 μm or lower in arithmetic average roughness Ra, 2.5 μm or lower in ten-point average roughness Rzjis, 2.0 μm or smaller in maximum height Rz, and 0.5 μm or lower in arithmetic average waviness Wa; and

a bonding step of bonding a semiconductor element to the semiconductor element-mounting section of the conductor portion.

12. The method for manufacturing a semiconductor circuit board according to claim 11 , wherein the surface treatment step is a polishing step.

13. The method for manufacturing a semiconductor circuit board according to claim 12 , wherein the polishing step is an etching step.

14. The method for manufacturing a semiconductor circuit board according to claim 12 , wherein the polishing step is a pressing process.

Assignments (4)
NUNC PRO TUNC ASSIGNMENT Recorded Feb 19, 2026
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MATERIALS CO. LTD.
Reel/Frame 074940/0511 →
CHANGE OF NAME Recorded Feb 19, 2026
From: TOSHIBA MATERIALS CO. LTD.
To: NITERRA MATERIALS CO., LTD.
Reel/Frame 074941/0803 →
CHANGE OF ADDRESS Recorded Feb 19, 2026
From: KABUSHIKI KAISHA TOSHIBA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 074941/0846 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2015
From: KATO, HIROMASA; HOSHINO, MASANORI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA MATERIALS CO., LTD.
Reel/Frame 035324/0750 →
Priority Claims (1)
JP 2012-222239 · Oct 4, 2012 · national
Continuity (1)
Related Publication 20150257252A1 · Sep 10, 2015