IP Library Granted Patent US 9,304,933
Granted Patent B2
US 9,304,933 · App. 13/976,109 · Granted Apr 5, 2016

Techniques to request stored data from a memory

Inventors: Kebing Wang (Shanghai, CN); Jun Ye (Shanghai, CN); Jianyu Li (Shanghai, CN)
Assignee: Intel Corporation
G06F12/0875G06F12/0886G06T1/60G06F8/4442G06F2212/302G06F2212/455G06F2212/601G06T15/04G09G5/39
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Quick Facts
Patent No.
US 9,304,933
App. No.
13/976,109
Granted
Apr 5, 2016
Kind
B2
Abstract

Techniques are described to configure a cache line structure based on attributes of a draw call and access direction of a texture. Attributes of textures (e.g., texture format and filter type), samplers, and shaders used by the draw call can be considered to determine the line size of a cache. Access direction can be considered to reduce the number of lines that are used to store texels required by a sample request.

Claims (36)

1. A computer-implemented method comprising:

determining a cache line size for a texture associated with a draw call based in part on a texture format attribute and texture filter type of a dominant texture;

selecting a tag from a group of one or more ways in a texture cache to compare to a received tag; and

in response to a tag match, providing data contents from one or more ways associated with the tag match based in part on the determined cache line size.

2. The method of claim 1 , wherein the texture format attribute specifies a texel size.

3. The method of claim 1 , wherein the texture filter type comprises point-sampling, linear-sampling, bilinear-sample, anisotropic-sampling, or MIPmap-sampling.

4. The method of claim 1 , wherein providing data contents from one or more ways associated with the tag match comprises:

determining a number of ways associated with the tag match so that data storable in the determined number of ways is as large or larger than the cache line size and

combining data contents from the determined number of ways.

5. The method of claim 1 , further comprising:

determining an access direction of the texture associated with the draw call and

requesting to store the texture in one or more ways based on the access direction so that contents of the texture are stored in a minimum number of ways.

6. A configurable texture cache, the cache comprising:

a plurality of ways, each way capable to store a block of data and a tag;

comparator logic to compare a received tag with a tag from one or more of the ways and to generate a cache hit or miss indicator;

combiner logic to selectively combine data from multiple ways, wherein a number of ways that are combined is based on a cache line size based in part on a texture format attribute and texture filter type of a dominant texture, and wherein the combiner logic provides a block of data or multiple sets of combined data;

logic to provide a set of combined data in response to a received tag matching a tag from the set of combined data or to provide a block of data in response to a received tag matching a tag associated with a single way; and

a processor to control which way releases a tag to the comparator logic and to control whether a block of data or combined data is output from the logic to provide a set of combined data.

7. The cache of claim 6 , wherein the logic to provide selects a set of combined data to provide based in part on the set being associated with a tag that matched a receive tag.

8. The cache of claim 6 , wherein the texture format attribute specifies a texel size and the texture filter type comprises point-sampling, linear-sampling, bilinear-sample, anisotropic-sampling, or MIPmap-sampling.

9. The cache of claim 6 , further comprising:

a memory controller to request data from memory for storage in one or more ways based on the cache line size and in response to a miss indicator.

10. The cache of claim 9 , wherein the processor is to determine an access direction of a texture and configure the memory controller to store the requested data into one or more ways while minimizing a number of ways used for storage.

11. The cache of claim 6 , wherein the size of a cache line is configured by combining data from multiple ways.

12. A system comprising:

an antenna;

a radio;

a texture cache having multiple ways, wherein multiple cache line sizes are accessible from the texture cache by combination of data from one or more ways;

a processor configured to determine a cache line size based in part on a texture format attribute and texture filter type of a dominant texture associated with a draw call, wherein the texture cache is to:

select a tag from a group of one or more ways in the texture cache to compare to a received tag and

in response to a tag match, access data contents from one or more ways associated with the tag match based in part on the determined cache line size.

13. The system of claim 12 , wherein the texture format attribute specifies a texel size and the texture filter type comprises point-sampling, linear-sampling, bilinear-sample, anisotropic-sampling, or MIPmap-sampling.

14. The system of claim 12 , wherein the texture cache is also configured to:

determine an access direction of a texture associated with the draw call and

request to store the texture in one or more ways of the texture cache based on the access direction so that contents of the texture are stored in a minimum number of ways.

15. The system of claim 12 , wherein a number of ways combined to form a cache line size is based on the number of bytes in the cache line size being equal to or less than a combined number of bytes in the combined number of ways.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072915/0599 →
Continuity (1)
Related Publication 20140028693A1 · Jan 30, 2014