IP Library Granted Patent US 9,324,821
Granted Patent B2
US 9,324,821 · App. 13/664,745 · Granted Apr 26, 2016

Compound semiconductor device and manufacturing method of the same

Inventor: Kozo Makiyama (Kawasaki, JP)
Assignee: FUJITSU LIMITED
H01L29/42316H01L29/0661H01L29/0843H01L29/2003H01L29/66462H01L29/7787
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Quick Facts
Patent No.
US 9,324,821
App. No.
13/664,745
Granted
Apr 26, 2016
Kind
B2
Abstract

An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure.

Claims (31)

1. A compound semiconductor device, comprising:

a substrate;

a nitride compound semiconductor stacked structure formed on or above the substrate; and

a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure,

wherein

the compound semiconductor stacked structure comprises:

a nitride electron transit layer;

a nitride electron supply layer formed on or above the nitride electron transit layer; and

a nitride surface layer formed on or above the nitride electron supply layer,

the nitride surface layer comprises:

a GaN lower layer;

an AlGaN intermediate layer formed on the GaN lower layer; and

a GaN upper layer formed on the AlGaN intermediate layer, and

a recess comprising a plurality of depths formed at the nitride surface layer between the drain electrode and an end portion of the gate electrode on the drain electrode side in a plan view,

wherein a first one of the plurality of depths is not less than a total thickness of the GaN upper layer and the AlGaN intermediate layer and not more than a total thickness of the GaN upper layer, the AlGaN intermediate layer and the GaN lower layer,

wherein the first one of the plurality of depths extends through the GaN upper layer, through the AlGaN intermediate layer, and partially through the GaN lower layer.

2. The compound semiconductor device according to claim 1 , wherein

a gate recess is formed at a surface of the compound semiconductor stacked structure, and

a part of the gate electrode is positioned in the gate recess.

3. A manufacturing method of a compound semiconductor device, comprising:

forming a nitride compound semiconductor stacked structure on or above a substrate, the forming of the compound semiconductor stacked structure comprising:

forming a nitride electron transit layer;

forming a nitride electron supply layer on or above the nitride electron transit layer; and

forming a nitride surface layer on or above the nitride electron supply layer, and the forming of the nitride surface layer comprising:

forming a GaN lower layer;

forming an AlGaN intermediate layer on the GaN lower layer; and

forming a GaN upper layer on the AlGaN intermediate layer;

forming a gate electrode, a source electrode and a drain electrode on or above the compound semiconductor stacked structure; and

forming a recess comprising a plurality of depths at the nitride surface layer between the drain electrode and an end portion of the gate electrode on the drain electrode side in a plan view,

wherein a first one of the plurality of depths is not less than a total thickness of the GaN upper layer and the AlGaN intermediate layer and not more than a total thickness of the GaN upper layer, the AlGaN intermediate layer and the GaN lower layer,

wherein the first one of the plurality of depths extends through the GaN upper layer, through the AlGaN intermediate layer, and partially through the GaN lower layer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2012
From: MAKIYAMA, KOZO
To: FUJITSU LIMITED
Reel/Frame 029280/0814 →
Priority Claims (1)
JP 2011-268237 · Dec 7, 2011 · national
Continuity (1)
Related Publication 20130146889A1 · Jun 13, 2013