Resistive random access memory (RRAM) structure

1. A resistive random access memory (RRAM) cell, comprising:

a transistor having a gate and a source/drain region;

a bottom electrode having an upper surface coplanar with a top surface of the gate;

a resistive material layer on the bottom electrode;

a top electrode on the resistive material layer; and

a conductive material connecting the bottom electrode to the source/drain region.

2. The RRAM cell of claim 1 , wherein the conductive material is a stretch contact free from a connection to a metal layer above the RRAM cell.

3. The RRAM cell of claim 2 , further comprising:

a bit line contact between the source region and a first metal layer,

wherein the bit line contact and the stretch contact comprise a same material and thickness.

4. The RRAM cell of claim 1 , wherein the bottom electrode and the gate comprise a same material and thickness.

5. The RRAM cell of claim 1 , wherein the bottom electrode and the gate comprise polysilicon.

6. The RRAM cell of claim 1 , wherein the bottom electrode and the gate comprise aluminum, titanium, titanium nitride, or tantalum nitride.

7. The RRAM cell of claim 1 , further comprising:

a gate dielectric between the bottom electrode and an underlying substrate.

8. The RRAM cell of claim 7 , further comprising:

shallow trench isolation (STI) regions in the substrate; and

a doped region in the substrate,

wherein the bottom electrode is over the STI regions and the doped region.

9. The RRAM cell of claim 1 , wherein the resistive material layer comprises hafnium oxide, zirconium oxide, aluminum oxide, nickel oxide, tantalum oxide or titanium oxide.

10. The RRAM cell of claim 1 , wherein a width of the top electrode is approximately equal to a width of the gate.

11. A resistive random access memory (RRAM) cell comprising:

a transistor comprising:

a gate connected to a word line; and

a source/drain region; and

an RRAM structure comprising:

a bottom electrode electrically connected to the source/drain region;

a resistive material layer over the bottom electrode; and

a top electrode over the resistive material layer, wherein the top electrode is connected to a source line;

wherein a first spacer surrounds the gate; and

a second spacer surrounds the bottom electrode.

12. The RRAM cell of claim 11 , further comprising:

a salicide over the source/drain region.

13. The RRAM cell of claim 11 , further comprising:

a salicide over the gate and over the bottom electrode.

14. The RRAM cell of claim 11 , further comprising:

a bit line contact electrically connected to the source contact.

15. The RRAM cell of claim 11 , wherein the bottom electrode and the gate comprise a same material and thickness.

16. The RRAM cell of claim 11 , wherein the bottom electrode comprises polysilicon.

17. The RRAM cell of claim 11 , further comprising:

shallow trench isolation (STI) regions in an underlying substrate,

wherein the bottom electrode is over the STI regions.

18. A memory cell array, comprising:

a first resistive random access memory (RRAM) cell; and

a second RRAM cell coupled with the first the first RRAM cell,

wherein the first RRAM cell and the second RRAM cell each comprise:

a transistor having a source/drain region,

a bottom electrode adjacent to the source/drain region,

a resistive material layer on the bottom electrode,

a top electrode on the resistive material layer, and

a conductive material connecting the bottom electrode to the source/drain region, and

the top electrode of the first RRAM cell extends to the top electrode of the second RRAM cell, coupling the first RRAM cell with the second RRAM cell.

19. The memory cell array of claim 18 , further comprising:

a third RRAM cell coupled with one of the first RRAM cell or the second RRAM cell by a bit line.

20. The RRAM cell of claim 11 , wherein the gate and the bottom electrode are coplanar.