Granted Patent B2

US 9,373,621 · App. 13/746,477 · Granted Jun 21, 2016

Abstract

Claims (26)

1. An analog integrated circuit comprising:

an analog circuit cell array including a plurality of transistor cells arranged in an array, each of the transistor cells comprising:

a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in a first direction one adjacent to another; and

a first gate electrode and a second gate electrode arranged on the first channel region and the second channel region, respectively, and the first gate electrode and the second gate electrode being extended in a second direction perpendicular to the first direction;

wherein the analog integrated circuit comprises a transistor pair arranged in a common centroid configuration by using 2*2 transistor cells located in a center area of the array in which the transistor cells are arranged, such that the first gate electrode and the second gate electrode of a given transistor cell in the 2*2 transistor cells are connected to the first gate electrode and the second gate electrode of another transistor cell arranged diagonally from the given transistor cell, and

wherein the first gate electrode and the second gate electrode of a transistor of the transistor pair are connected to a common drain region of a transistor cell, of the plurality of transistor cells, located outside of the center area of the array, and

wherein a first gate electrode, a second gate electrode, a first source region and a second source region of the transistor cell, of the plurality of transistor cells, located outside of the center area of the array, are connected together.

2. An analog integrated circuit comprising:

an analog circuit cell array including a plurality of transistor cells arranged in an array, each of the transistor cells comprising:

a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in a first direction one adjacent to another; and

a first gate electrode and a second gate electrode arranged on the first channel region and the second channel region, respectively, and the first gate electrode and the second gate electrode being extended in a second direction perpendicular to the first direction;

wherein the analog integrated circuit comprises a transistor pair arranged in a common centroid configuration by using 2*2 transistor cells located in a center area of the array in which the transistor cells are arranged, such that the first gate electrode and the second gate electrode of a given transistor cell in the 2*2 transistor cells are connected to the first gate electrode and the second gate electrode of another transistor cell arranged diagonally from the given transistor cell, and

wherein the first gate electrode and the second gate electrode of a first transistor of the transistor pair are connected to a common drain region of a first transistor cell, of the plurality of transistor cells, located outside of the center area of the array, and

wherein the first gate electrode and the second gate electrode of a second transistor of the transistor pair are connected to the common drain region of a second transistor cell, of the plurality of transistor cells, located outside of the center area of the array.

3. The analog integrated circuit according to claim 2 , wherein the each transistor cell includes an interconnecting electrode for interconnecting the first gate electrode and the second gate electrode.

4. The analog integrated circuit according to claim 2 , wherein the first gate electrode and the second gate electrode of the each transistor cell extend outwardly of the first channel region and the second channel region, respectively, and are provided with interconnect contacts on outwardly extending portions.

5. The analog integrated circuit according to claim 2 , further comprising: a diffusion region extending in the first direction, arranged along a boundary area extending in the first direction of the each transistor cell, for feeding a well in the each transistor cell.

6. The analog integrated circuit according to claim 2 , further comprising metal interconnect lines, wherein the metal interconnect lines are not placed above the first channel region and the second channel region of any transistor cell.

7. The analog integrated circuit according to claim 2 , wherein the plurality of transistor cells includes PMOS transistor cells and NMOS transistor cells.

8. The analog integrated circuit according to claim 3 , wherein the plurality of transistor cells includes PMOS transistor cells and NMOS transistor cells.

9. The analog integrated circuit according to claim 4 , wherein the plurality of transistor cells includes PMOS transistor cells and NMOS transistor cells.

10. The analog integrated circuit according to claim 5 , wherein the plurality of transistor cells includes PMOS transistor cells and NMOS transistor cells.

11. The analog integrated circuit according to claim 6 , wherein the plurality of transistor cells includes PMOS transistor cells and NMOS transistor cells.

12. The analog integrated circuit according to claim 2 , wherein the first gate electrode and the second gate electrode of each of two transistor cells contained in a transistor of the transistor pair are connected to each other through a first connection wiring located in a first wiring layer.

13. The analog integrated circuit according to claim 2 , wherein the first gate electrode and the second gate electrode of the first transistor of the transistor pair are connected to the common drain region of the first transistor cell through a second connection wiring located in the first wiring layer.

14. The analog integrated circuit according to claim 2 , wherein the transistor cells are arranged in four or more rows and four or more columns.

Assignments (8)