A memory device includes a bit line extending in a first direction, a word line extending in a second direction crossing the first direction, an insulating material between the word line and another word line, a first layer made of a Group IV element, between the word line and the insulating material and between the word line and the bit line, and a second layer made of a compound of a Group V element and a Group VI element, between the insulating material and the bit line. The word line includes a first portion that is metallic and a second portion between the first portion and the first layer. In addition, a variable resistance portion in contact with the first and second layers and the second portion of the word line, contains the Group IV element and the compound of the Group V element and the Group VI element.
1. A memory device comprising:
a plurality of bit lines, including first and second bit lines, extending in a first direction away from a substrate;
a plurality of word lines, including first and second word lines, extending in a second direction crossing the first direction and substantially parallel to a surface of the substrate;
an insulating material between the first and second word lines;
a first layer made of a Group IV element, between the first word line and the insulating material and between the first word line and the first bit line; and
a second layer made of a compound of a Group V element and a Group VI element, between the insulating material and the first bit line, wherein
the first word line includes a first portion that is metallic and a second portion between the first portion and the first layer, and
a variable resistance portion in contact with the first and second layers and the second portion of the first word line, contains the Group IV element and the compound of the Group V element and the Group VI element.
2. The device according to claim 1 , further comprising:
an oxide layer between the first layer and the first bit line.
3. The device according to claim 1 ,
wherein the first bit line is made of tungsten and the oxide layer is made of tungsten oxide.
4. The device according to claim 1 ,
wherein the first layer contains an element of one species selected from a group including germanium, silicon and carbon, and
wherein the second layer contains one of an antimony-tellurium alloy or a bismuth-tellurium alloy.
5. The device according to claim 1 , wherein a resistivity of the first layer is higher than a resistivity of the second layer.
6. The device according to claim 1 , wherein the second portion is a barrier metal layer.
7. The device according to claim 1 , wherein
the plurality of bit lines are evenly spaced apart in the second direction and in a third direction that intersects both the first direction and the second direction; and
the plurality of word lines are evenly spaced apart in the first direction and two word lines are arranged on opposite sides of each bit line in the third direction.
8. The device according to claim 1 ,
wherein the variable resistance portion is in a first state when the Group IV element locally exists in the compound of the Group V element and the Group VI element, and a second state when the Group V element is diffusely distributed in the compound of the Group V element and the Group VI element.
9. A memory device comprising:
a plurality of bit lines, including first and second bit lines, extending in a first direction away from a substrate;
a plurality of word lines, including first and second word lines, extending in a second direction crossing the first direction and substantially parallel to a surface of the substrate;
an insulating material between the first and second word lines;
a first layer between the first word line and the insulating material;
a second layer between the insulating material and the first bit line, and
a variable resistance layer between the first word line and the first bit line, wherein
the first word line includes a first portion that is metallic and a second portion between the first portion and the first layer and the first portion and the variable resistance layer, and
the variable resistance layer is in contact with the first and second layers, the second portion of the first word line, and the bit line, and contains a Group IV element and a compound of a Group V element and a Group VI element.
10. The device according to claim 9 , wherein the first layer is made of the Group IV element, and the second layer is made of the compound of the Group V element and the Group VI element.
11. The device according to claim 9 , wherein the first layer is made of the compound of the Group V element and the Group VI element, and the second layer is made of the Group IV element.
12. The device according to claim 9 , wherein the variable resistance layer contains germanium, antimony and tellurium.
13. The device according to claim 9 , wherein a resistivity of the first layer is higher than a resistivity of the second layer.
14. The device according to claim 9 , wherein
the plurality of bit lines are evenly spaced apart in the second direction and in a third direction that intersects both the first direction and the second direction; and
the plurality of word lines are evenly spaced apart in the first direction and two word lines are arranged on opposite sides of each bit line in the third direction.
15. The device according to claim 9 ,
wherein the variable resistance layer is in a first state when the Group IV element locally exists in the compound of the Group V element and the Group VI element, and a second state when the Group V element is diffusely distributed in the compound of the Group V element and the Group VI element.
16. A memory device comprising:
a plurality of bit lines, including first and second bit lines, extending in a first direction away from a substrate;
a plurality of word lines, including first and second word lines, extending in a second direction crossing the first direction and substantially parallel to a surface of the substrate;
a first insulating layer between the first and second word lines;
a Group IV element layer made of a Group IV element between the first word line and the first bit line; and
a second insulating layer between a first portion of the first word line and the Group IV element layer but not between a second portion of the first word line and the Group IV element layer, wherein a thickness of the first portion is greater than a thickness of the second portion.
17. The device according to claim 16 , wherein
a second portion of the first word line is in direct contact with the Group IV element layer.
18. The device according to claim 16 , further comprising:
a variable resistance portion between the second portion of the first word line and the Group IV element layer.
19. The device according to claim 18 , wherein the variable resistance portion contains the Group IV element and a compound of a Group V element and a Group VI element.
20. The device according to claim 16 , wherein
the plurality of bit lines are evenly spaced apart in the second direction and in a third direction that intersects both the first direction and the second direction, each of the bit lines being sandwiched by two Group IV element layers in the third direction; and
the plurality of word lines are evenly spaced apart in the first direction and the third direction.