IP Library Granted Patent US 9,465,640
Granted Patent B2
US 9,465,640 · App. 14/483,534 · Granted Oct 11, 2016

Information processing apparatus and method of controlling information processing apparatus

Inventor: Hirobumi Yamaguchi (Kawasaki, JP)
Assignee: FUJITSU LIMITED
G06F9/45558G06F2009/45579
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Quick Facts
Patent No.
US 9,465,640
App. No.
14/483,534
Granted
Oct 11, 2016
Kind
B2
Abstract

An information processing apparatus includes: a VM including a driver that is configured to perform data input/output using an input/output device; a hypervisor configured to manage the VM and perform a synchronization process between the information processing apparatus and another information processing apparatus which form a pair; a monitoring unit configured to monitor an access made between a memory and the input/output device; a notification unit configured to notify the hypervisor of detection of a reading access in a case where the reading access relating to data output from the memory to the input/output device is detected by the monitoring unit; and a suppression unit configured to suppress the data output in a case where the hypervisor is in the middle of execution of the synchronization process when the hypervisor receives the notification from the notification unit. Accordingly, the input/output access performance of the VM is improved.

Claims (46)

1. An information processing apparatus comprising a processor that builds:

a virtual machine including a driver that performs data input/output using an input/output device; and

a hypervisor that manages the virtual machine and performs a synchronization process between the information processing apparatus and another information processing apparatus which form a pair,

wherein the processor

monitors an access made between a memory and the input/output device;

notifies the hypervisor of detection of a reading access in a case where the reading access relating to data output from the memory to the input/output device is detected by the monitoring; and

suppresses the data output from the memory to the input/output device, in a case where the hypervisor is during execution of the synchronization process when the hypervisor receives the notification, to prevent a synchronization state between the information processing apparatus and another information processing apparatus from being interrupted,

wherein the information processing apparatus includes an interrupt factor flag configured to be set in a case where the processor generates an interrupt having detection of the reading access as a factor so as to cause the hypervisor to perform the synchronization process and to be cleared when the hypervisor ends the synchronization process,

wherein the processor determines that the hypervisor is during execution of the synchronization process in a case where the interrupt factor flag is set and determines that the hypervisor is not during execution of the synchronization process in a case where the interrupt factor flap is not set.

2. The information processing apparatus according to claim 1 , wherein the processor releases the suppression of the data output when the hypervisor ends the synchronization process.

3. The information processing apparatus according to claim 1 , wherein the reading access is issuance of a reading request from the input/output device to the memory or reading of target data of the data output from the memory to the input/output device.

4. The information processing apparatus according to claim 3 , wherein the processor suppresses the data output by temporarily maintaining the reading request or the target data in a buffer and, when the hypervisor ends the synchronization process, transmits the reading request from the buffer to a side of the memory or transmits the target data from the buffer to the input/output device.

5. The information processing apparatus according to claim 1 ,

wherein the processor, in a case where a writing access relating to data writing from the input/output device to the memory is detected, records an occurrence of a change in data corresponding to an address relating to the data writing in a table for managing the memory, and

wherein the hypervisor performs the synchronization process in accordance with the table.

6. The information processing apparatus according to claim 5 ,

wherein the processor records the occurrence of the change by setting a change bit in the table, and

wherein the hypervisor clears the change bit when the synchronization process ends.

7. The information processing apparatus according to claim 1 , further the processor

counts a number of portions of the memory in which a change in data occurs by a counter;

stores a count value acquired by the counter that is referred to at the time of the synchronization process of a previous time in a storage area;

compares in a case where the hypervisor is not during execution of the synchronization process when the hypervisor receives the notification, the value of the counter with the count value stored in the storage area and,

suppresses, in a case where the value of the counter and the count value stored in the storage area do not coincide with each other, the data output to cause the hypervisor to perform the synchronization process.

8. The information processing apparatus according to claim 7 , wherein the processor, in a case where the value of the counter and the count value stored in the storage area coincide with each other, performs the data output without suppressing the data output.

9. A method comprising:

in an information processing apparatus that includes a processor that builds a virtual machine including a driver that performs data input/output using an input/output device and a hypervisor that manages the virtual machine and performs a synchronization process between the information processing apparatus and another information processing apparatus which form a pair, monitoring an access made between a memory and the input/output device;

notifying the hypervisor of detection of a reading access in a case where the reading access relating to data output from the memory to the input/output device is detected in the monitoring of an access; and

suppressing the data output from the memory to the input/output device, in a case where the hypervisor is during execution of the synchronization process when the hypervisor receives the notification, to prevent a synchronization state between the information processing apparatus and another information processing apparatus from being interrupted,

wherein the information processing apparatus includes an interrupt factor flag configured to be set in a case where an interrupt having detection of the reading access as a factor is generated so as to cause the hypervisor to perform the synchronization process and to be cleared when the hypervisor ends the synchronization process,

wherein the hypervisor is determined to be during execution of the synchronization process in a case where the interrupt factor flag is set, and the hypervisor is determined not to be during execution of the synchronization process in a case where the interrupt factor flag is not set.

10. The method of controlling an information processing apparatus according to claim 9 , wherein the suppression of the data output is released when the hypervisor ends the synchronization process.

11. The method of controlling an information processing apparatus according to claim 9 , wherein the reading access is issuance of a reading request from the input/output device to the memory or reading of target data of the data output from the memory to the input/output device.

12. The method of controlling an information processing apparatus according to claim 11 ,

wherein the data output is suppressed by temporarily maintaining the reading request or the target data in a buffer, and

wherein, when the hypervisor ends the synchronization process, the reading request is transmitted from the buffer to a side of the memory, or the target data is transmitted from the buffer to the input/output device.

13. The method of controlling an information processing apparatus according to claim 9 ,

wherein, in a case where a writing access relating to data writing from the input/output device to the memory is detected in the monitoring of an access, an occurrence of a change in data corresponding to an address relating to the data writing is recorded in a table for managing the memory, and

wherein the hypervisor performs the synchronization process in accordance with the table.

14. The method of controlling an information processing apparatus according to claim 13 ,

wherein the occurrence of a change is recorded by setting the change bit in the table, and

wherein the hypervisor clears the change bit when the synchronization process ends.

15. The method of controlling an information processing apparatus according to claim 9 , the method further comprising:

counting a number of portions of the memory in which a change in data occurs by a counter; and

storing a count value acquired by the counter that is referred to at the time of the synchronization process of a previous time in a storage area,

wherein, in a case where the hypervisor is not during execution of the synchronization process when the hypervisor receives the notification, the value of the counter is compared with the count value stored in the storage area, and, in a case where the value of the counter and the count value stored in the storage area do not coincide with each other, the suppression of the data output is performed, and the hypervisor is caused to perform the synchronization process.

16. The method of controlling an information processing apparatus according to claim 15 , wherein, in a case where the value of the counter and the count value stored in the storage area coincide with each other, the data output is performed without suppressing the data output.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ORIGINAL COVER SHEET BY REMOVING PATENT NUMBER 10586039 PREVIOUSLY RECORDED ON REEL 69272 FRAME 546. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 1, 2025
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 070764/0091 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2024
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 069272/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2014
From: YAMAGUCHI, HIROBUMI
To: FUJITSU LIMITED
Reel/Frame 033818/0728 →
Priority Claims (1)
JP 2013-228182 · Nov 1, 2013 · national
Continuity (1)
Related Publication 20150128137A1 · May 7, 2015