Systems and methods for sensing current while minimizing measurement error and power loss
View Patent ↗A method may include deactivating a switch of a measurement circuit during a measurement portion of at least one voltage regulator phase, wherein each of the at least one voltage regulator phase is integral to a voltage regulator and each of the at least one voltage regulator phase comprises a power stage. The power stage may include a high-side switch for delivering electrical current to the at least one information handling resource in conformity with a first duty cycle of the high-side switch. The power stage may also include a low-side switch for sinking electrical current to an electrical ground in conformity with a second duty cycle of the low-side switch. The method may also include measuring a voltage across a sense resistor of the measurement circuit during the measurement portion, wherein the sense resistor is coupled in parallel with non-gate terminals of the switch.
1. An information handling system comprising:
at least one information handling resource;
a voltage regulator coupled to the at least one information handling resource, the voltage regulator comprising at least one voltage regulator phase having a power stage comprising:
a high-side switch for delivering electrical current to the at least one information handling resource in conformity with a first duty cycle of the high-side switch, the first duty cycle defining a duration of time in which the high-side switch is activated; and
a low-side switch for sinking electrical current to an electrical ground in conformity with a second duty cycle of the low-side switch, the second duty cycle defining a duration of time in which the low-side switch is activated;
a measurement circuit for measuring an electrical current delivered to the voltage regulator, the measurement circuit comprising:
a sense resistor; and
a switch, wherein non-gate terminals of the switch are coupled in parallel with the sense resistor; and
a control circuit configured to, during a measurement portion of at least one of the first duty cycle and the second duty cycle of the at least one voltage regulator phase:
deactivate the switch of the measurement circuit; and
measure a voltage across the sense resistor.
2. The information handling system of claim 1 , wherein the control circuit is further configured to deactivate the switch of the measurement circuit during portions of the first duty cycle and second duty cycle outside of the measurement portion.
3. The information handling system of claim 1 , wherein the control circuit is further configured to control the first duty cycle of each high-side switch and the second duty cycle of each low-side switch.
4. The information handling system of claim 1 , wherein the measurement portion occurs during a period of each first duty cycle or each second duty cycle in which the current is substantially linear as a function of time.
5. The information handling system of claim 1 , wherein the measurement portion occurs during a period of each first duty cycle or each second duty cycle in which current ringing is not present in the current.
6. The information handling system of claim 1 , wherein the measurement portion is approximately centered in the first duty cycle or second duty cycle.
7. A method comprising:
deactivating a switch of a measurement circuit during a measurement portion of at least one voltage regulator phase, wherein:
each of the at least one voltage regulator phase is integral to a voltage regulator; and
each of the at least one voltage regulator phase comprises a power stage having:
a high-side switch for delivering electrical current to the at least one information handling resource in conformity with a first duty cycle of the high-side switch, the first duty cycle defining a duration of time in which the high-side switch is activated; and
a low-side switch for sinking electrical current to an electrical ground in conformity with a second duty cycle of the low-side switch, the second duty cycle defining a duration of time in which the low-side switch is activated; and
measuring a voltage across a sense resistor of the measurement circuit during the measurement portion, wherein the sense resistor is coupled in parallel with non-gate terminals of the switch.
8. The method of claim 7 , further comprising deactivating the switch of the measurement circuit during portions of the first duty cycle and second duty cycle outside of the measurement portion of the duty cycle.
9. The method of claim 7 , wherein the measurement portion occurs during a period of each first duty cycle or second duty cycle in which the current is substantially linear as a function of time.
10. The method of claim 7 , wherein the measurement portion occurs during a period of each first duty cycle and each second duty cycle in which current ringing is not present in the current.
11. The method of claim 7 , wherein the measurement portion is approximately centered in the first duty cycle or the second duty cycle.
12. A voltage regulator comprising:
at least one voltage regulator phase having a power stage comprising;
a high-side switch for delivering electrical current to the at least one information handling resource in conformity with a first duty cycle of the high-side switch, the first duty cycle defining a duration of time in which the high-side switch is activated; and
a low-side switch for sinking electrical current to an electrical ground in conformity with a second duty cycle of the low-side switch, the second duty cycle defining a duration of time in which the low-side switch is activated;
a measurement circuit for measuring an electrical current delivered to the voltage regulator, the measurement circuit comprising:
a sense resistor; and
a switch, wherein non-gate terminals of the switch are coupled in parallel with the sense resistor; and
a control circuit configured to, during a measurement portion of the first duty cycle or the second duty cycle of the at least one voltage regulator phase:
deactivate the switch of the measurement circuit; and
measure a voltage across the sense resistor.
13. The voltage regulator of claim 12 , wherein the control circuit is further configured to deactivate the switch of the measurement circuit during portions of the first duty cycle and the second duty cycle outside of the measurement portion.
14. The voltage regulator of claim 12 , wherein the control circuit is further configured to control the first duty cycle and the second duty cycle.
15. The voltage regulator of claim 12 , wherein the measurement portion of each first duty cycle and each second duty cycle occurs during a period in which the current is substantially linear as a function of time.
16. The voltage regulator of claim 12 , wherein the measurement portion occurs during a period of each first duty cycle or each second duty cycle in which current ringing is not present in the current.
17. The voltage regulator of claim 12 , wherein the measurement portion is approximately centered in the first duty cycle or the second duty cycle.