IP Library Granted Patent US 9,484,455
Granted Patent B2
US 9,484,455 · App. 14/978,194 · Granted Nov 1, 2016

Isolation NLDMOS device and a manufacturing method therefor

Inventors: Donghua Liu (Shanghai, CN); Wenting Duan (Shanghai, CN); Wensheng Qian (Shanghai, CN)
Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
H01L29/7823H01L29/1095H01L29/66681
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Quick Facts
Patent No.
US 9,484,455
App. No.
14/978,194
Granted
Nov 1, 2016
Kind
B2
Abstract

An isolation NLDMOS device including: an N well and a P well adjacent to each other on an upper part of a P substrate; on the upper part of the P well are sequentially arranged a first P type heavily doped region, a first field oxide, and a second P type heavily doped region; on the upper part of the N well are arranged a second field oxide and an N type heavily doped region; a gate oxide is between the second P type heavily doped region and the second field oxide; a gate polysilicon sits above the gate oxide and part of the second field oxide; from the first P type heavily doped region, the second P type heavily doped region and the N type heavily doped region are led out each a connecting wire via a respective contact hole.

Claims (21)

1. An isolation NLDMOS device, comprising:

an N well and a P well adjacent to each other on an upper part of a P type substrate, wherein the P well is situated inside a deep N well, one side of the deep N well being underneath an arc side of the N well adjoining the P well; on an upper part of the P well is sequentially arranged a first P type heavily doped region, a first field oxide, and a second P type heavily doped region; on an upper part of the N well are arranged a second field oxide and an N type heavily doped region; a gate oxide is between the second P type heavily doped region and the second field oxide on the upper parts of the P well and the N well respectively; a gate polysilicon sits above the gate oxide and a part of the second field oxide; and a connecting wire is led out via a contact hole respectively from the first P type heavily doped region, the second P type heavily doped region and the N type heavily doped region.

2. The isolation NLDMOS device of claim 1 , wherein a doping concentration of the N well is between 5 12 cm −2 and 3 13 cm −2 .

3. The isolation NLDMOS device of claim 1 , wherein a doping concentration of the first P type heavily doped region and of the second P type heavily doped region is between 1 15 cm −2 and 3 15 cm −2 .

4. The isolation NLDMOS device of claim 1 , wherein a doping concentration of the N type heavily doped region is between 1 15 cm −2 and 3 15 cm −2 .

5. The isolation NLDMOS device of claim 1 , wherein a doping concentration of the P well is between 1 12 cm −2 and 2 13 cm −2 .

6. The isolation NLDMOS device of claim 1 , wherein a doping concentration of the deep N well is between 1 12 cm −2 and 2 13 cm −2 .

7. A manufacturing method for the isolation NLDMOS device, the method comprising:

1) forming a deep N well on a P type substrate via implanting N ions;

2) forming a first field oxide on the deep N well via etching, and forming a second field oxide on the P type substrate via etching;

3) forming a P well via implanting P ions inside the deep N well, and forming an N well on the P type substrate via implanting N ions, wherein the P well and the N well are adjacent to each other, and one side of the deep N well being underneath an arc side of the N well adjoining the P well;

4) growing a gate oxide via thermal oxidation;

5) depositing a polysilicon, and forming a gate polysilicon therefrom via etching;

6) forming a first P type heavily doped region and a second P type heavily doped region via implanting heavily doped P ions on both sides of the first field oxide;

7) forming an N type heavily doped region by implanting heavily doped N ions into the N well on a side of the second field oxide farthest from the first field oxide; and

8) leading forth a connecting wire from the first P type heavily doped region, the second P type heavily doped region and the N type heavily doped region via a respective contact hole.

8. The manufacturing method for the isolation NLDMOS device of claim 7 , wherein a doping concentration for manufacturing the first P type heavily doped region and the second P type heavily doped region is between 1 15 cm −2 and 3 15 cm −2 .

9. The manufacturing method for the isolation NLDMOS device of claim 7 , wherein a doping concentration for manufacturing the N type heavily doped region is between 1 15 cm −2 and 3 15 cm −2 .

10. The manufacturing method for the isolation NLDMOS device of claim 7 , wherein a doping concentration for manufacturing the P well is between 1 12 cm −2 and 2 13 cm −2 .

11. The manufacturing method for the isolation NLDMOS device of claim 7 , wherein a doping concentration for manufacturing the deep N well is between 1 12 cm −2 and 2 13 cm −2 .

12. The manufacturing method for the isolation NLDMOS device of claim 7 , wherein a doping concentration for manufacturing the N well is between 5 12 cm −2 and 3 13 cm −2 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2015
From: LIU, DONGHUA; DUAN, WENTING; QIAN, WENSHENG
To: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 037349/0795 →
Priority Claims (1)
CN 2015 1 0067904 · Feb 10, 2015 · national
Continuity (1)
Related Publication 20160233332A1 · Aug 11, 2016