Nonvolatile memory devices and methods of fabricating the same

1. A nonvolatile memory device, comprising:

a vertically-stacked gate structure including a plurality of inter-gate insulating patterns stacked on a substrate and a plurality of gate electrodes interposed between the inter-gate insulating patterns in an alternating gate electrode and insulating pattern sequence;

a vertical active pillar extending at least partially through the vertically-stacked gate structure;

a vertical charge-storing layer extending between the vertical active pillar and the plurality of gate electrodes;

a vertical tunnel insulating layer extending between the vertical charge-storing layer and the vertical active pillar; and

a vertical blocking insulating layer extending between the vertical charge-storing layer and the plurality of gate electrodes;

wherein the vertical charge-storing layer comprises a first charge-storing layer containing silicon nitride adjacent to the vertical blocking insulating layer and a second charge-storing layer adjacent to the vertical tunnel insulating layer, said second charge-storing layer comprising silicon oxynitride;

wherein the vertical tunnel insulating layer comprises a first tunnel insulating layer adjacent to the second charge-storing layer and a second tunnel insulating layer adjacent to the vertical active pillar; and

wherein the first tunnel insulating layer comprises a silicon oxide layer having a nitrogen concentration therein that is lower than a nitrogen concentration within the second charge-storing layer.

2. The nonvolatile memory device of claim 1 , wherein the second charge-storing layer has a thickness less than 20 Å.

3. The nonvolatile memory device of claim 1 , wherein the second tunnel insulating layer comprises silicon oxide; and wherein a nitrogen concentration within the second tunnel insulating layer is greater than the nitrogen concentration within the first tunnel insulating layer and less than the nitrogen concentration within the second charge-storing layer.

4. The nonvolatile memory device of claim 1 , wherein each of the first and second tunnel insulating layers contains about 5 atomic percent to about 20 atomic percent nitrogen; and wherein the second charge-storing layer contains at least about 30 atomic percent nitrogen.

5. The nonvolatile memory device of claim 1 , wherein the vertical blocking insulating layer comprises a first vertical blocking insulating layer adjacent to the vertical charge-storing layer and a second vertical blocking insulating layer adjacent to the plurality of gate electrodes.

6. The nonvolatile memory device of claim 5 , wherein the first vertical blocking insulating layer and the second vertical blocking insulating layer comprise silicon oxide and aluminum oxide, respectively.

7. The nonvolatile memory device of claim 5 , wherein at least a portion of the vertical blocking insulating layer extends between the plurality of gate electrodes and the plurality of inter-gate insulating patterns.

8. The nonvolatile memory device of claim 7 , wherein at least a portion vertical charge-storing layer extends between the plurality of gate electrodes and the plurality of inter-gate insulating patterns.

9. A nonvolatile charge trap memory cell, comprising:

a tunnel insulating layer on a semiconductor active region;

a charge-storing layer on the tunnel insulating layer;

a blocking insulating layer on the charge-storing layer; and

a gate electrode on the blocking insulating layer;

wherein said charge storing layer comprises a first charge-storing layer contacting the blocking insulating layer and a second charge-storing layer contacting the tunnel insulating layer, said first charge-storing layer comprising silicon nitride and said second charge-storing layer comprising silicon oxynitride and having a thickness in a range from about 5 Å to about 20 Å, wherein the thickness of the second charge-storing layer is less than about 20 Å.

10. The memory cell of claim 9 , wherein the charge-storing layer extends between the tunnel insulating layer and the blocking insulating layer;

wherein the blocking insulating layer extends between the charge-storing layer and the gate electrode;

wherein the tunnel insulating layer extends between the charge-storing layer and the semiconductor active region and contains about 5 atomic percent to about 20 atomic percent nitrogen; and

wherein the second charge-storing layer contains at least about 30 atomic percent nitrogen.

11. A nonvolatile memory device, comprising:

a gate electrode;

an active layer;

a charge-storing layer between the active layer and the gate electrode;

a tunnel insulating layer between the charge-storing layer and the active layer; and

a blocking insulating layer between the charge-storing layer and the gate electrode,

wherein the charge-storing layer comprises a first charge-storing layer adjacent to the blocking insulating layer and a second charge-storing layer adjacent to the tunnel insulating layer;

wherein the first charge-storing layer comprises a silicon nitride layer, and wherein the second charge-storing layer comprises a silicon oxynitride layer; and

wherein the blocking insulating layer comprises a first blocking insulating layer adjacent to the charge-storing layer and a second blocking insulating layer adjacent to the gate electrode.

12. The nonvolatile memory device of claim 11 , wherein the tunnel insulating layer comprises a first tunnel insulating layer adjacent to the second charge-storing layer and a second tunnel insulating layer adjacent to the active layer, and

wherein the first tunnel insulating layer comprises a silicon oxide layer having a nitrogen concentration that is lower than a nitrogen concentration of the second charge-storing layer.

13. The nonvolatile memory device of claim 12 , wherein the second tunnel insulating layer comprises a silicon oxide layer having a nitrogen concentration that is between the nitrogen concentrations of the first tunnel insulating layer and the second charge-storing layer.

14. The nonvolatile memory device of claim 11 , wherein the tunnel insulating layer contains about 5 at. % to about 20 at. % nitrogen, and the second charge-storing layer contains at least about 30 at. % nitrogen.

15. The nonvolatile memory device of claim 11 , wherein the

second charge-storing layer has a thickness less than 20 Å.

16. The nonvolatile memory device of claim 11 , wherein the first blocking insulating layer comprises a silicon oxide layer, and the second blocking insulating layer comprises an aluminum oxide layer.

17. The nonvolatile memory device of claim 11 ,

wherein the gate electrode comprises one gate electrode among a plurality of gate electrodes,

wherein the nonvolatile memory device further comprises a vertically-stacked gate structure including a plurality of inter-gate insulating patterns stacked on a substrate and the plurality of gate electrodes interposed between the inter-gate insulating patterns in an alternating gate electrode and insulating pattern sequence,

wherein at least a portion of the blocking insulating layer extends between the plurality of gate electrodes and the inter-gate insulating patterns.

18. The nonvolatile memory device of claim 11 ,

wherein the gate electrode comprises one gate electrode among a plurality of gate electrodes,

wherein the nonvolatile memory device further comprises a vertically-stacked gate structure including a plurality of inter-gate insulating patterns stacked on a substrate and the plurality of gate electrodes interposed between the inter-gate insulating patterns in an alternating gate electrode and insulating pattern sequence,

wherein at least a portion of the blocking insulating layer extends between the active layer and the inter-gate insulating patterns.

19. The nonvolatile memory device of claim 11 ,

wherein the gate electrode comprises one gate electrode among a plurality of gate electrodes,

wherein the nonvolatile memory device further comprises a vertically-stacked gate structure including a plurality of inter-gate insulating patterns stacked on a substrate and the plurality of gate electrodes interposed between the inter-gate insulating patterns in an alternating gate electrode and insulating pattern sequence,

wherein at least a portion of the charge-storing layer extends between the plurality of gate electrodes and the inter-gate insulating patterns.

20. The nonvolatile memory device of claim 11 ,

wherein the gate electrode comprises one gate electrode among a plurality of gate electrodes,

wherein the nonvolatile memory device further comprises a vertically-stacked gate structure including a plurality of inter-gate insulating patterns stacked on a substrate and the plurality of gate electrodes interposed between the inter-gate insulating patterns in an alternating gate electrode and insulating pattern sequence,

wherein at least a portion of the charge-storing layer extends between the active layer and the inter-gate insulating patterns.