Systems and methods for reducing memory failures

1. A method for in-system repair of a memory failure, the method comprising:

initiating operation of a memory;

detecting, by the memory, a failure;

determining, by the memory, if the failure is correctable or uncorrectable;

upon determining the failure is correctable, performing a correctable error repair process;

upon determining the failure is uncorrectable, performing an uncorrectable error repair process;

communicating a fail status and information through a channel connecting the memory and a System on Chip (SoC);

testing a failure address and a target repair row without an external device; and

executing, by the SoC, a repair process by the SoC.

2. The method of claim 1 , wherein detecting the failure includes detecting a random bit failure in the memory.

3. The method of claim 1 , wherein the memory is a dynamic random access memory.

4. The method of claim 1 , wherein the uncorrectable error repair process further comprises:

storing at least one of the failure address, available repair steps, or an error flag;

reading information related to the failure; and

executing repair instructions.

5. The method of claim 4 , wherein reading the information related to the failure includes determining if data at the failure address is stored in a first memory location.

6. The method of claim 4 , executing the repair instructions further comprises:

entering a temporary programming mode;

executing a programming entry command; and

exiting the temporary programming mode.

7. The method of claim 6 , further comprising:

determining if data at the failure address is stored in a first memory location;

upon determining if the data is stored, writing the data in a second memory location; and

upon determining if the data is not stored is the first memory location, writing pattern data in the second memory location.

8. The method of claim 7 , wherein the second memory location is tested to verify the writing pattern data.

9. The method of claim 6 , further comprising:

determining if the uncorrectable error repair process is successful;

upon determining the uncorrectable error repair process is not successful, invalidating the uncorrectable error repair process and one of executing a second programming entry command or generating a system fail call; and

upon determining the uncorrectable error repair process is successful, continuing the operation of the memory.

10. The method of claim 9 , wherein continuing the operation of the memory further comprises:

testing at least a portion of the memory; and

restarting the operation of the memory.

11. The method of claim 1 , wherein the uncorrectable error repair process further comprises:

storing at least one of the failure address, available repair steps, and an error flag;

reading information related to the failure in the memory;

stopping the operation of the memory; and

executing repair instructions.

12. The method of claim 11 , wherein a system on chip component stops the operation of the memory and the memory executes the repair instructions.

13. The method of claim 11 , further comprising:

sending programming commands to the memory; and

initiating programming commands using the stored failure address and available redundancy information.

14. The method of claim 13 , further comprising storing the programming commands in first and second memory locations.

15. The method of claim 14 , wherein the first and second memory locations are tested to verify the storing the programming commands.

16. The method of claim 15 , further comprising:

determining if the uncorrectable error repair process is successful;

upon determining the uncorrectable error repair process is not successful, invalidating the uncorrectable error repair process and generating a system fail call; and

upon determining the uncorrectable error repair process is successful, continuing the operation of the memory.

17. The method of claim 16 , wherein continuing the operation of the memory further comprises:

testing at least a portion of the memory; and

restarting the operation of the memory.

18. A method for in-system repair of a memory failure, the method comprising:

initiating operation of a memory;

detecting, by the memory, a failure;

determining, by the memory, if the failure is one of a correctable failure or an uncorrectable failure;

upon detecting the correctable failure, performing a correctable error repair process;

communicating a fail status and information through a channel connecting the memory and a System on Chip (SoC);

testing a failure address and a target repair row without an external device; and

executing, by the SoC, a repair process.

19. The method of claim 18 , further comprising:

upon detecting the uncorrectable failure, performing the following:

storing at least one of the failure address, available repair steps, or an error flag;

performing a data scrub operation;

determining if the data scrub operation is successful;

upon determining the data scrub operation is successful; returning to continued operation of the memory; and

upon determining the data scrub operation is unsuccessful, executing repair instructions.

20. The method of claim 19 , further comprising:

determining if the failure is repeated;

upon determining the failure is not repeated, returning to continued operation of the memory; and

upon determining the failure is repeated, executing the repair instructions.

21. The method of claim 18 , further comprising:

storing at least one of the failure address, available repair steps, or an error flag; and

reading the failure address and failure data.

22. The method of claim 21 , further comprising storing the failure data in a second memory location.

23. The method of claim 22 , further comprising testing the failure address and the failure data to determine if the failure is corrected.

24. The method of claim 22 , further comprising:

entering a temporary programming mode;

executing a programming entry command; and

exiting the temporary programming mode.

25. The method of claim 24 , further comprising:

storing memory data;

writing the memory data in the second memory location; and

testing the second memory location to verify the writing the memory data.

26. The method of claim 25 , further comprising:

determining if the correctable error repair process is successful;

upon determining the correctable error repair process is not successful, invalidating the correctable error repair process and executing a second programming entry command; and

upon determining the correctable error repair process is successful, continuing the operation of the memory.

27. The method of claim 26 , wherein continuing the operation of the memory further comprises testing at least a portion of the memory.

28. A memory system, comprising:

a memory configured to detect a failure, determine if the failure is correctable or uncorrectable;

a system on chip component, the system on chip component configured to communicate with the memory;

a repair process component configured to perform an in-system repair of correctable and uncorrectable memory failures and test a failure address and a target repair row without an external device.

29. A non-transitory machine readable medium comprising machine readable instructions that, when executed by a processor, cause the processor to:

initiate operation of a memory;

detect, by the memory, a failure;

determine, by the memory, if the failure is correctable or uncorrectable;

upon determining the failure is correctable, perform a correctable error repair process;

upon determining the failure is uncorrectable, perform an uncorrectable error repair process;

communicate a fail status and information through a channel connecting the memory and a System on Chip (SoC);

testing a failure address and a target repair row without an external device; and

executing, by the SoC, a repair process by the SoC.