Integrating a planar field effect transistor (FET) with a vertical FET

1. A method of integrating a planar field-effect transistor (FET) with a vertical FET, comprising:

masking and etching a first semiconductor of the vertical FET to form a fin;

providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region of the vertical FET;

depositing spacer dielectric on the bottom S/D region to form a spacer on the bottom S/D region;

etching back the fin to expose one or more vertical sections of the fin;

depositing gate metals on the first semiconductor and a second semiconductor of the planar FET;

etching a vertical gate for the vertical FET and a planar gate for the planar FET from the gate metals deposited using a shared gate mask, wherein the vertical gate is perpendicular to and extends across the first semiconductor, and the planar gate is perpendicular to and extends across the second semiconductor;

forming a gate dielectric isolating the second semiconductor from the planar gate by removing a portion of spacer and replacing the portion of the spacer removed with a high voltage gate dielectric layer;

depositing dielectric on the fin;

etching the dielectric deposited on the fin to expose one or more portions of the fin;

growing epitaxy on the one or more exposed portions of the fin;

masking and etching contact openings for contacts of the vertical FET and the planar FET;

forming silicide regions in S/D regions of the vertical FET and source and drain regions of the planar FET;

depositing contact metal in the silicide regions to form the contacts of the vertical FET and the planar FET; and

planarizing the contacts of the vertical FET and the planar FET.

2. The method of claim 1 , further comprising:

isolating the bottom S/D region using one or more implants.

3. The method of claim 1 , wherein:

removing a portion of spacer comprises removing a portion of the spacer in a planar region; and

the high voltage gate dielectric layer is a separate, planar-specific gate dielectric for the planar region.

4. The method of claim 1 , wherein etching the dielectric deposited on the fin to expose one or more portions of the fin comprises exposing a top of the fin.

5. The method of claim 1 , wherein growing epitaxy on the one or more exposed portions of the fin comprises growing epitaxy on a top S/D region of the vertical FET, and the fin connects the epitaxy in the top S/D region to the bottom S/D region.

6. The method of claim 1 , further comprising:

forming the spacer using a reactive ion etching (RIE) process, wherein a gate contact for the vertical gate is masked using the shared gate mask during the RIE process.

7. The method of claim 1 , wherein the vertical FET and the planar FET share the silicide regions and the contacts.

8. The method of claim 1 , further comprising:

implanting the bottom S/D region in a vertical region and a planar region, such that the planar region and the vertical region share the bottom S/D region.

9. The method of claim 1 , wherein a top of the vertical gate and a top of the planar gate are co-planar.

10. The method of claim 1 , wherein the bottom S/D region is co-planar with an active region of the planar FET.