IP Library Granted Patent US 9,502,978
Granted Patent B2
US 9,502,978 · App. 14/593,820 · Granted Nov 22, 2016

Switched power stage and a method for controlling the latter

Inventors: Hassan Ihs (Vendargues, FR); Taner Dosluoglu (New York, NY)
Assignee: Endura Technologies LLC
H02M3/158
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Quick Facts
Patent No.
US 9,502,978
App. No.
14/593,820
Granted
Nov 22, 2016
Kind
B2
Abstract

The disclosure relates to a method of generating an output voltage, comprising: generating a regulated output voltage from a high voltage source; providing an inductor having a first terminal and a second terminal linked to a low voltage source by a capacitor, the second inductor terminal supplying the output voltage to a load; connecting the first inductor terminal exclusively either to the high voltage source or to the low voltage source or to the second inductor terminal, as a function of command signals to reduce a difference between the output voltage and a reference voltage lower than a high voltage supplied by the high voltage source; and generating a square binary control signal having a duty cycle substantially adjusted to the ratio of the output voltage to the high voltage; the first inductor terminal being connected to the high voltage source or to the low voltage source as a function of a binary state of the control signal.

Claims (34)

1. A switching regulator with a reference pulse width modulation (PWM) reference circuitry, comprising:

switches for coupling a first terminal of an output inductor alternatively to a supply voltage or to ground based on a duty cycle signal, the output inductor having a second terminal coupled to ground by a capacitor and providing a voltage output signal;

reference switches for coupling an input of a circuit including a reference capacitor alternatively to the supply voltage or to ground based on the duty cycle signal, the reference capacitor coupled to ground;

an error amplifier for amplifying a difference between an output of the circuit including the reference capacitor and a reference voltage;

a waveform generator for generating a periodic waveform having a period based on a clock signal; and

a first comparator for comparing the periodic waveform and an output of the error amplifier, an output of the comparator providing the duty cycle signal.

2. The switching regulator of claim 1 , wherein the circuit including a reference capacitor comprises a low pass filter.

3. The switching regulator of claim 2 , wherein the low pass filter is a first order circuit.

4. The switching regulator of claim 1 , where the waveform generator is a sawtooth signal generator.

5. The switching regulator of claim 1 , further comprising a second comparator for comparing the voltage output signal to the reference voltage, and wherein the switches additionally operate based on an output of the second comparator.

6. The switching regulator of claim 5 , further comprising logic circuitry configured for generating signals to control the switches based on the duty cycle signal and the output of the second comparator.

7. The switching regulator of claim 6 , further comprising a bypass switch for selectively coupling the first terminal of the output inductor to the second terminal of the output inductor.

8. The switching regulator of claim 7 , wherein the logic circuitry is additionally configured for controlling the bypass switch based on the output of the second comparator.

9. A method of generating a regulated voltage, comprising:

providing an inductor having a first terminal and a second terminal linked to a low voltage source by a capacitor, the second inductor terminal supplying a regulated output voltage to a load;

connecting the first inductor terminal exclusively either to a high voltage source or to the low voltage source or to the second inductor terminal, as a function of command signals to reduce a difference between the output voltage and a reference voltage lower than the high voltage; and

generating a binary control signal using a reference circuit, the binary control signal having a duty cycle substantially adjusted to the ratio of the output voltage to a high voltage supplied by the high voltage source, the first inductor terminal being connected to the high voltage source or to the low voltage source as a function of a binary state of the control signal.

10. A method of generating a regulated voltage, comprising:

providing an inductor having a first terminal and a second terminal linked to a low voltage source by a capacitor, the second inductor terminal supplying a regulated output voltage to a load;

connecting the first inductor terminal exclusively either to a high voltage source or to the low voltage source or to the second inductor terminal, as a function of command signals to reduce a difference between the output voltage and a reference voltage lower than the high voltage; and

generating a binary control signal using a reference circuit, the binary control signal having a duty cycle substantially adjusted to the ratio of the output voltage to a high voltage supplied by the high voltage source, the first inductor terminal being connected to the high voltage source or to the low voltage source as a function of a binary state of the control signal;

wherein generating the control signal comprises:

low-pass filtering a square wave signal to obtain a filtered signal;

generating an amplified error signal resulting from a comparison of the filtered signal with the reference voltage; and

forming the control signal based on a comparison of the amplified error signal and a periodic wave form signal.

11. A switched power stage providing a regulated output voltage, the power stage comprising:

an inductor having a first inductor terminal and a second inductor terminal forming an output of the power stage,

a switching device linking the first inductor terminal exclusively either to a high voltage source, or to a low voltage source, or to the second inductor terminal,

a capacitor linking the second inductor terminal to the low voltage source, and

a control circuit configured to control the switching device as a function of a high voltage supplied by the high voltage source and the output voltage, to reduce a difference between the output voltage and a reference voltage lower than the high voltage, the control circuit including a reference circuit configured to generate a square binary control signal having a duty cycle substantially adjusted to the ratio of the reference voltage to the high voltage, and the control circuit configured to control the switching device to connect the first inductor terminal either to the high voltage source or to the low voltage source as a function of a binary state of the control signal.

12. The power stage according to claim 11 , wherein the reference circuit comprises:

a pulse width modulation generator configured to generate the control signal having a duty cycle adjusted as a function of an amplified error signal;

a low-pass filter filtering a signal based on the control to obtain a filtered signal;

an error amplifier configured to generate the amplified error signal from a comparison of the filtered signal with the reference voltage.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2023
From: CHAOYANG SEMICONDUCTOR (SHANGHAI) CO., LTD.
To: ENDURA IP HOLDINGS LTD.
Reel/Frame 063424/0226 →
CHANGE OF NAME Recorded Mar 29, 2022
From: CHAOYANG SEMICONDUCTOR JIANGYIN TECHNOLOGY CO., LTD.
To: CHAOYANG SEMICONDUCTOR (SHANGHAI) CO., LTD
Reel/Frame 061088/0212 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2018
From: ENDURA IP HOLDINGS LTD.
To: ENDURTECH (HONG KONG) LIMITED
Reel/Frame 045987/0673 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2018
From: ENDURTECH (HONG KONG) LIMITED
To: CHAOYANG SEMICONDUCTOR JIANGYIN TECHNOLOGY CO. LTD.
Reel/Frame 045989/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2018
From: ENDURA TECHNOLOGIES LLC
To: ENDURA IP HOLDINGS LTD.
Reel/Frame 045931/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2015
From: IHS, HASSAN; DOSLUOGLU, TANER
To: ENDURA TECHNOLOGIES LLC
Reel/Frame 035418/0933 →
Continuity (2)
Provisional Application 62037063 · Aug 13, 2014
Related Publication 20160049860A1 · Feb 18, 2016