IP Library Granted Patent US 9,542,321
Granted Patent B2
US 9,542,321 · App. 14/260,463 · Granted Jan 10, 2017

Slice-based random access buffer for data interleaving

Inventors: Zhiwei Wu (Shanghai, CN); Zhibin Li (Shanghai, CN); Kurt J. Worrell (Berthoud, CO); Joseph R. Robert (Bethlehem, PA); Feina Wen (Shanghai, CN)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
G06F12/084G06F3/0608G06F3/0644G06F3/0656G06F3/0665G06F3/0689G06F3/061G06F3/064G06F12/0871G06F2003/0691G06F2003/0692G06F2212/1044G06F2212/152G06F2212/165G06F2212/21G06F2212/222G06F2212/224G06F2212/251G06F2212/262G06F2212/281G06F2212/282G06F2212/312G06F2212/462G06F2212/6042G06F2212/70G06F2212/7203G11B20/10527
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Quick Facts
Patent No.
US 9,542,321
App. No.
14/260,463
Granted
Jan 10, 2017
Kind
B2
Abstract

The disclosure is directed to a system and method for interleaving data utilizing a random access buffer that includes a plurality of independently accessible memory slots. The random access buffer is configured to store slices of incoming data sectors in free memory slots, where a free memory slot is identified by a status flag associated with a logical address of the free memory slot. Meanwhile, a label buffer is configured to store labels associated with the slices of the incoming data sectors in a sequence based upon an interleaving scheme. Media sectors including the interleaved data slices are read out from the memory slots of the random access buffer in order of the sequence of labels stored by the label buffer. As the media sectors are read out of the random access buffer, the corresponding memory slots are freed up for incoming slices of the next super-sector.

Claims (38)

1. A system for interleaving data, comprising:

a slice divider configured to receive incoming data sectors of a super-sector,

the slice divider being further configured to divide the incoming data sectors into slices;

a random access buffer including memory slots for storing data sector slices, the random access buffer being configured to store the slices of the incoming data sectors in free memory slots, wherein a free memory slot is identified by a status flag associated with a logical address of the free memory slot;

a label buffer configured to store labels associated with the slices of the incoming data sectors in a sequence based upon an interleaving scheme; and

a processor in communication with the random access buffer and the label buffer, the processor being configured to read out media sectors corresponding to the super-sector, wherein a media sector includes interleaved data slices read out from the memory slots of the random access buffer in order of the sequence of labels stored by the label buffer.

2. The system of claim 1 , wherein the processor is configured to read out the media sectors corresponding to the super-sector after determining that the memory slots of the random access buffer for storing the data sector slices have been filled.

3. The system of claim 1 , wherein the memory slots of the random access buffer for storing the data sector slices include at least enough memory slots to store each slice of each sector of a super-sector including a pre-determined largest possible number of sectors.

4. The system of claim 1 , wherein the memory slots of the random access buffer for storing the data sector slices are the same size.

5. The system of claim 1 , wherein each of the memory slots of the random access buffer for storing the data sector slices is at least as large as a pre-determined largest possible slice of a data sector.

6. The system of claim 5 , wherein each of the memory slots of the random access buffer for storing the data sector slices is configured for receiving differently sized slices of a logical sector.

7. The system of claim 1 , wherein the interleaving scheme is programmable.

8. The system of claim 1 , wherein the processor is further configured to read out the media sectors corresponding to the super-sector after a predetermined delay period to ensure gapless output when variably sized super-sectors are being processed.

9. A method of interleaving data, comprising:

receiving incoming data sectors of a super-sector;

dividing the incoming data sectors into slices;

storing the slices of the incoming data sectors in free memory slots of a plurality of independently accessible memory slots, wherein a free memory slot is identified by a status flag associated with a logical address of the free memory slot;

storing labels associated with the slices of the incoming data sectors in a sequence based upon an interleaving scheme; and

reading out media sectors corresponding to the super-sector, wherein a media sector includes interleaved data slices read out from the plurality of independently accessible memory slots in order of the sequence of stored labels.

10. The method of claim 9 , wherein the media sectors corresponding to the super-sector are read out after determining that the independently accessible memory slots for storing data sector slices have been filled.

11. The method of claim 9 , wherein the media sectors corresponding to the super-sector are read out after a predetermined delay period to ensure gapless output when variably sized super-sectors are being processed.

12. The method of claim 9 , wherein the independently accessible memory slots for storing data sector slices include at least enough memory slots to store each slice of each sector of a super-sector including a pre-determined largest possible number of sectors.

13. The method of claim 9 , wherein the independently accessible memory slots for storing data sector slices are the same size.

14. The method of claim 9 , wherein each of the independently accessible memory slots for storing data sector slices is at least as large as a pre-determined largest possible slice of a data sector.

15. The method of claim 14 , wherein each of the independently accessible memory slots for storing data sector slices is configured for receiving differently sized slices of a logical sector.

16. A storage device, comprising:

a storage medium; and

a storage controller, the storage controller being configured to transfer data to the storage medium via a write channel, the write channel including:

a slice divider configured to receive incoming data sectors of a super-sector being written to the storage medium, the slice divider being further configured to divide the incoming data sectors into slices;

a random access buffer including memory slots for storing data sector slices, the random access buffer being configured to store the slices of the incoming data sectors in free memory slots, wherein a free memory slot is identified by a status flag associated with a logical address of the free memory slot; and

a label buffer configured to store labels associated with the slices of the incoming data sectors in a sequence based upon an interleaving scheme, the storage controller being in communication with the random access buffer and the label buffer, the storage controller being configured to transfer media sectors corresponding to the super-sector to the storage medium, wherein a media sector includes interleaved data slices read out from the memory slots of the random access buffer in order of the sequence of labels stored by the label buffer.

17. The storage device of claim 16 , wherein the memory slots of the random access buffer for storing the data sector slices include at least enough memory slots to store each slice of each sector of a super-sector including a pre-determined largest possible number of sectors.

18. The storage device of claim 16 , wherein each of the memory slots of the random access buffer for storing the data sector slices is at least as large as a pre-determined largest possible slice of a data sector.

19. The storage device of claim 16 , wherein the storage controller is further configured to retrieve data from the storage medium via a read channel, the read channel including:

a slice divider configured to receive incoming media sectors of a super-sector being read from the storage medium, the slice divider being further configured to divide the incoming media sectors into slices;

a random access buffer including memory slots for storing media sector slices, the random access buffer being configured to store the slices of the incoming media sectors in free memory slots, wherein a free memory slot is identified by a status flag associated with a logical address of the free memory slot; and

a label buffer configured to store labels associated with the slices of the incoming media sectors in a sequence based upon a de-interleaving scheme, the de-interleaving scheme being based upon the interleaving scheme of the write channel, the storage controller being configured to read out data sectors of the super-sector being read from the storage medium, wherein a data sector includes de-interleaved data slices read out from the memory slots of the random access buffer in order of the sequence of labels stored by the label buffer.

20. The storage device of claim 16 , wherein the storage controller is further configured to receive instructions from a redundant array of independent disks (RAID) controller, the RAID controller being in further communication with a plurality of storage devices included with the storage device in a RAID storage cluster.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2014
From: WU, ZHIWEI; LI, ZHIBIN; WORRELL, KURT J.; ROBERT, JOSEPH R.; WEN, FEINA
To: LSI CORPORATION
Reel/Frame 032746/0093 →
Continuity (1)
Related Publication 20160034393A1 · Feb 4, 2016