Systems and methods for providing replicated data from memories to processing clients
Systems and methods are provided for a network device. A device includes a plurality of packet processing clients. The device further includes a plurality of memories, where a quantity of the memories is greater than a quantity of the packet processing clients, each of the memories storing a replica of data, the packet processing clients being configured to selectively read the control data from any of the memories. An arbiter is configured to select in a first clock cycle for the plurality of packet processing clients a first subset of memories from among the plurality of memories from which to read the control data, and in a second clock cycle, subsequent to the first clock cycle, to select for the plurality of packet processing clients a second subset of memories from among the plurality of memories from which to read the control data.
1. A network device that receives packet data from a network, comprising:
a plurality of packet processing clients for processing packet data received from a network;
a plurality of memories, wherein a quantity of the memories is greater than a quantity of the packet processing clients, each of the memories storing a replica of same control data to be used by the packet processing clients, the packet processing clients being configured to selectively read the control data from any of the memories; and
an arbiter coupled to the packet processing clients and to the memories, the arbiter being configured to select in a first clock cycle for the plurality of packet processing clients a first subset of memories from among the plurality of memories from which to read the control data, and in a second clock cycle, subsequent to the first clock cycle, to select for the plurality of packet processing clients a second subset of memories from among the plurality of memories from which to read the control data, the second subset of memories including at least some memories that are not included in the first subset of memories.
2. The network device of claim 1 , wherein the second subset of memories does not include at least one memory that is in the first subset of memories.
3. The network device of claim 1 , wherein the arbiter comprises a first shift register containing an entry for each of the packet processing clients that is configured to identify an order according to which the packet processing clients are assigned memories for access during a particular clock cycle, and wherein the arbiter is configured to determine a starting memory from which to map memories for assignment to the packet processing clients in the order identified by the first shift register.
4. The network device of claim 3 , wherein the arbiter is configured to determine the starting memory using a modulo operation that is based on a number of packet processing clients in the plurality of packet processing clients and a number of memories in the plurality of memories.
5. The network device of claim 4 , wherein the arbiter is configured to determine the starting memory according to:
Starting Memory=(cycle* N )% M,
where cycle is a clock cycle number, N is the number of packet processing clients, % represents a modulo operation, and M is the number of memories.
6. The network device of claim 3 , wherein the shift register is configured to shift the packet processing clients X positions per clock cycle.
7. The network device of claim 1 , wherein during the first clock cycle where a first memory is assigned to a first packet processing client, when the first packet processing client has a read request and the first memory is not busy with a prior read request or otherwise unable to execute the read request, the first processing client is configured to read data from the first memory.
8. The network device of claim 1 , wherein the device is one of a bridge, a router, a switch or other network device.
9. The network device of claim 1 , wherein the packet processing clients are disposed on an electrical circuit substrate, and wherein the memories are external to the electrical circuit substrate.
10. The network device of claim 9 , wherein the memories are implemented using a technology that does not permit read operations in consecutive clock cycles to a same memory location or region.
11. A method of providing control data to a plurality of packet processing clients configured to process packet data received by a network, comprising:
updating a plurality of M memories with same replicated control data to be used by a plurality of N packet processing clients, where M is greater than N;
using an arbiter to assign to each of the packet processing clients one of the memories from among the M memories for accessing the control data during a first clock cycle, each packet processing client being assigned a different one of the memories from among the M memories, wherein at least one of the memories among the M memories is a first unassigned memory that is not assigned to a packet processing client during the first clock cycle;
using the arbiter to assign to each of the processing clients a different memory from among the M memories for accessing the control data during a second clock cycle, wherein at least one of the memories among the M memories is a second unassigned memory that is not assigned to a packet processing client during the second clock cycle, the second unassigned memory being different from the first unassigned memory.
12. The method of claim 11 , wherein at least one of the memories among the M memories assigned to a packet processing client in the first clock cycle is not assigned to a packet processing client in the second clock cycle.
13. The method of claim 11 , wherein assigning one of the memories to each of the packet processing clients for the first clock cycle comprises:
using a first shift register that contains an entry for each of the packet processing clients to determine a first packet processing client to be assigned a memory.
14. The method of claim 13 , wherein assigning one of the memories to each of the packet processing clients for the first clock cycle further comprises:
determining a first memory to be assigned based on a modulo operation that is based on a number of packet processing clients N in the plurality of packet processing clients and a number of memories M in the plurality of memories.
15. The method of claim 14 , wherein the first memory is determined according to:
Starting Memory=(cycle* N )% M,
where cycle is a clock cycle number, N is the number of packet processing clients, % represents a modulo operation, and M is the number of memories.
16. The method of claim 14 , wherein assigning one of the memories to each of the packet processing clients for the second clock cycle comprises:
shifting the entries in the shift register X positions; and
using the shifted entries in the first shift register to determine a first packet processing client to be assigned a memory.
17. The method of claim 11 , wherein during the first clock cycle where a first memory is assigned to a first packet processing client, when the first packet processing client has a read request and the first memory is not busy with a prior read request or otherwise unable to execute the read request, the first processing client reads data from the first memory.
18. The method of claim 11 , further comprising:
disposing the packet processing clients on an electrical circuit substrate;
providing memories that are external to the electrical circuit substrate, and coupling the external memories 3 the packet processing clients that are disposed on the electrical circuit substrate.
19. The method of claim 18 , wherein providing the memories comprises providing memories that are implemented using a technology that does not permit read operations in consecutive clock cycles to a same memory location or region.
20. A network switch device, comprising:
a first electrical circuit substrate comprising:
a plurality of packet processing clients for processing packet data received from a network;
a plurality of memories, wherein a quantity of the memories is greater than a quantity of the packet processing clients, each of the memories storing a replica of same control data to be used by the packet processing clients, the packet processing clients being configured to selectively read the control data from any of the memories; and
an arbiter disposed on the first electrical substrate coupled to the packet processing clients and to the memories, the arbiter being configured to select in a first clock cycle for the plurality of packet processing clients a first subset of memories from among the plurality of memories from which to read the control data, and in a second clock cycle, subsequent to the first clock cycle, to select for the plurality of packet processing clients a second subset of memories from among the plurality of memories from which to read the control data, the second subset of memories including at least some memories that are not included in the first subset of memories.