Bandgap reference circuit with curvature compensation
View Patent ↗A bandgap reference circuit with curvature compensation. The circuit includes a first current mirror that mirrors the current conducted by the bandgap reference. A difference between the gate-to-source voltages in the two legs provides a first mirrored current with non-linear temperature stability. This first mirrored current is again mirrored by a second current mirror in which the mirror transistors also have differing gate-to-source voltages, with the current from this second current mirror coupled to the bandgap reference to compensate for curvature in the CTAT current over temperature.
1. A reference circuit, comprising:
a first circuit branch comprising a bipolar transistor and a resistor connected in series with a conduction path of the bipolar transistor between a common node and a ground voltage;
a second circuit branch comprising a bipolar transistor and a pair of resistors connected in series with a conduction path of the bipolar transistor between the common node and the ground voltage;
a current control transistor having a conduction path and a gate;
a first resistor connected to the common node and in series with the conduction path of the current control transistor;
an amplifier having inputs coupled to nodes in the first and second circuit branches, and an output coupled to the gate of the current control transistor;
a first current mirror comprising:
a first mirror transistor, having a gate coupled to the output of the amplifier and the gate of the current control transistor, and having a conduction path connected on one side to the power supply voltage so that the first mirror transistor has a gate-to-source voltage different from that of the current control transistor; and
a second current mirror comprising:
a reference transistor having a gate and drain connected together and to another side of the conduction path of the first mirror transistor, and having a source;
a second mirror transistor having a drain connected to the common node, a gate connected to the gate and drain of the reference transistor, and a source connected to the ground voltage so that the second mirror transistor has a gate-to-source voltage different from that of the reference transistor.
2. The circuit of claim 1 , wherein the first current mirror further comprises:
a second resistor connected between the conduction path of the current control transistor and a power supply voltage, the second resistor establishing the gate-to-source voltage at the current control transistor as different from that of the first mirror transistor.
3. The circuit of claim 2 , wherein the second current mirror further comprises:
a third resistor connected between the source of the reference transistor and the ground voltage, the second resistor establishing the gate-to-source voltage at the reference transistor as different from that of the second mirror transistor.
4. The circuit of claim 2 , wherein the current mirror further comprises:
a fourth resistor connected between the conduction path of the first mirror transistor and the power supply voltage, the fourth resistor having a resistance different from that of the first transistor to establish the gate-to-source voltage of the first mirror transistor as different from that of the current control transistor.
5. The circuit of claim 1 , wherein the current control transistor and the first mirror transistor are each p-channel metal-oxide-semiconductor transistors.
6. The circuit of claim 5 , wherein the reference transistor and the second mirror transistor are each n-channel metal-oxide-semiconductor transistors.
7. The circuit of claim 1 , wherein one input of the amplifier is connected to a node between the conduction path of the bipolar transistor and the resistor in the first circuit branch;
and wherein another input of the amplifier is connected to a node between the pair of resistors in the second circuit branch.
8. The circuit of claim 1 , further comprising:
a third current mirror comprising:
a third mirror transistor, having a gate coupled to the output of the amplifier and the gate of the current control transistor, and having a conduction path connected on one side to the power supply voltage so that the third mirror transistor has a gate-to-source voltage different from that of the current control transistor; and
a fourth current mirror comprising:
a reference transistor having a gate and drain connected together and to another side of the conduction path of the first mirror transistor, and having a source;
a fourth mirror transistor having a drain connected to the common node, a gate connected to the gate and drain of the reference transistor, and a source connected to the ground voltage so that the fourth mirror transistor has a gate-to-source voltage different from that of the reference transistor.
a fifth resistor connected between the source of the reference transistor and the ground voltage, the fifth resistor establishing the gate-to-source voltage at the reference transistor as different from that of the fourth mirror transistor.
9. A method of generating a reference voltage, comprising:
conducting a first current through a current control transistor;
splitting the first current at a common node between first and second circuit branches, each including a bipolar transistor;
controlling a gate voltage of the current control transistor responsive to voltages at respective nodes in the first and second circuit branches;
biasing a first mirror transistor to have a different gate-to-source voltage than the current control transistor, the first mirror transistor having a gate connected to the gate of the current control transistor to produce a first mirror current; and
biasing a reference transistor and a second mirror transistor to have different gate-to-source voltages from one another, the reference transistor and second mirror transistor having gates connected to one another, the reference transistor having a source-drain path connected to receive the first mirror current, and the second mirror transistor having a source-drain path connected to the common node.
10. The method of claim 9 , wherein the step of biasing the first mirror transistor comprises:
conducting the first current through a resistor connected between the source of the current control transistor and a power supply voltage;
wherein the source of the first mirror transistor is connected to the power supply voltage.
11. The method of claim 9 , wherein the step of biasing the reference transistor and the second mirror transistor comprises:
conducting the first mirror current through a resistor connected between the source of the reference transistor and a ground voltage;
wherein the source of the second mirror transistor is connected to the ground voltage.
12. The method of claim 9 , further comprising:
obtaining a bandgap reference voltage at a drain node of the current control transistor.
13. The method of claim 9 , wherein the current control transistor and the first mirror transistor are each p-channel metal-oxide-semiconductor transistors;
and wherein the reference transistor and the second mirror transistor are each n-channel metal-oxide-semiconductor transistors.